Pin Efficient 1x32 Component Interface (Flipped) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Figure 1. Connections for a Pin Efficient 1x32 LPDDR4/4x Interface

Nibble utilization for pin efficient 1x32 interface using one x32 component in the flipped configuration is shown in the following figure. For maximum interface performance use the 1x32 pinout described in the Figure titled "Nibble utilization for 1x32 component interface (Flipped)". DQ indicates data nibbles, AC indicates Address/Command/Control nibbles, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble utilization for pin efficient 1x32 component interface (Flipped)