This section provides PCB designers with guidance on how to ensure their DDRMC pinout is sufficient when considering future memory topology expansions like additional ranks, slots, or transitioning to 3DS devices. The AMD Versal™ DDRMC pinout behavior is a departure from previous generations as each memory technology has a unique set of fixed pinouts and the final pin map is dependent on the memory topology and the expansion options. This section describes the different pinouts supported for different memory technologies, how they may change per the topology, and how to ensure the DDRMC pinout going to fabrication is correct with future expansion in mind.
Recommended: You are encouraged to try the Obtaining and Verifying Versal Adaptive SoC Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools may lead to hardware failures if pin rules are not followed.