Pinout Options for Future Expansion - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

This section provides PCB designers with guidance on how to ensure their DDRMC pinout is sufficient when considering future memory topology expansions like additional ranks, slots, or transitioning to 3DS devices. The Versal® DDRMC pinout behavior is a departure from previous generations as each memory technology has a unique set of fixed pinouts and the final pin map is dependent on the memory topology and the expansion options. This section describes the different pinouts supported for different memory technologies, how they may change per the topology, and how to ensure the DDRMC pinout going to fabrication is correct with future expansion in mind.