Pinout Rules - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Pinouts or pin mapping for DDR4 and LPDDR4/4X memory interfaces are fixed and are output by the Vivado® tools as per the selected configuration. Some pinout flexibility is provided for DQ bits within a byte and is described in the pin rules section. Even when following the pin rules the recommendation is to validate the final pinout in Vivado. Strict adherence to all documented PCB guidelines is required for successful operation. For more information on PCB guidelines, see the Versal ACAP PCB Design User Guide (UG863).
Important:

LPDDR4/4X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. Additionally the DQ mapping from the ACAP to the LPDDR4/4X component channels needs to maintain an exact one-to-one mapping. For example, LPDDR4_DQ_A[0] must be connected to DQ0 of Channel A of the LPDDR4 component, LPDDR4_DQ_A[1] must be connected to DQ1 of Channel A, through LPDDR4_DQ_B[15] that must be connected to DQ15 of Channel B of the LPDDR4 component. You are encouraged to try the Obtaining and Verifying Versal ACAP Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools may lead to hardware failures if pin rules are not followed.

Each DDRMC has three XPIO Banks (known as a triplet) associated with it. An XPIO Bank comprises twenty seven differential pin pairs (L0P/N to L26P/N). There are nine Nibbles in a Bank and each Nibble has six pins. The package pin name IO_NiPj_MxPy describes the fields listed below.

NiPj
Ni is the Nibble number within a Bank (where i = 0 to 8)

Pj is the pin number within the Nibble (where j = 0 to 5).

MxPy
Mx is the DDRMC triplet number (where x = 0 to (Total number of DDRMCs – 1))

Py is the pin number within the triplet (where y = 0 to 161).

  • MxP0 through MxP53 are pins in the first Bank of the triplet.
  • MxP54 through MxP107 are pins in the second Bank of the triplet.
  • MxP108 through MxP161 are pins in the third Bank of the triplet.
Table 1. Mapping of Triplet Pin to Nibble Pin in a Bank
Triplet#Pin# Nibble#Pin# in package pin name Notes
M0P0 IO_L0P_XCC_N0P0 First pin in first Bank of triplet maps to first pin of Nibble 0 Pin 0
M0P1 IO_L0N_XCC_N0P1
M0P2 IO_L1P_N0P2
M0P3 IO_L1N_N0P3
M0P4 IO_L2P_N0P4
M0P5 IO_L2N_N0P5 Last pin of Nibble 0 in this Bank
M0P6 IO_L3P_ XCC_N1P0 First pin of Nibble 1 in this Bank
M0P7 IO_L3N_ XCC_N1P1
M0P8 IO_L4P_N1P2
M0P9 IO_L4N_N1P3
M0P10 IO_L5P_N1P4
M0P11 IO_L5N_N1P5 Last pin of Nibble 1 in this Bank
M0P12 IO_L6P_ GC_XCC_N2P0 First pin of Nibble 2 in this Bank
M0P13 IO_L6N_ GC_XCC_N2P1
M0P14 IO_L7P_N2P2
M0P15 IO_L7N_N2P3
M0P16 IO_L8P_N2P4
M0P17 IO_L8N_N2P5 Last pin of Nibble 2 in this Bank
M0P18 IO_L9P_ GC_XCC_N3P0 First pin of Nibble 3 in this Bank
M0P19 IO_L9N_ GC_XCC_N3P1
M0P20 IO_L10P_N3P2
M0P21 IO_L10N_N3P3
M0P22 IO_L11P_N3P4
M0P23 IO_L11N_N3P5 Last pin of Nibble 3 in this Bank
M0P24 IO_L12P_ GC_XCC_N4P0 First pin of Nibble 4 in this Bank
M0P25 IO_L12N_ GC_XCC_N4P1
M0P26 IO_L13P_N4P2
M0P27 IO_L13N_N4P3
M0P28 IO_L14P_N4P4
M0P29 IO_L14N_N4P5 Last pin of Nibble 4 in this Bank
M0P30 IO_L15P_XCC_N5P0 First pin of Nibble 5 in this Bank
M0P31 IO_L15N_XCC_N5P1
M0P32 IO_L16P_N5P2
M0P33 IO_L16N_N5P3
M0P34 IO_L17P_N5P4
M0P35 IO_L17N_N5P5 Last pin of Nibble 5 in this Bank
M0P36 IO_L18P_XCC_N6P0 First pin of Nibble 6 in this Bank
M0P37 IO_L18N_XCC_N6P1
M0P38 IO_L19P_N6P2
M0P39 IO_L19N_N6P3
M0P40 IO_L20P_N6P4
M0P41 IO_L20N_N6P5 Last pin of Nibble 6 in this Bank
M0P42 IO_L21P_XCC_N7P0 First pin of Nibble 7 in this Bank
M0P43 IO_L21N_XCC_N7P1
M0P44 IO_L22P_N7P2
M0P45 IO_L22N_N7P3
M0P46 IO_L23P_N7P4
M0P47 IO_L23N_N7P5 Last pin of Nibble 7 in this Bank
M0P48 IO_L24P_GC_XCC_N8P0 First pin of Nibble 8 in this Bank
M0P49 IO_L24N_GC_XCC_N8P1
M0P50 IO_L25P_N8P2
M0P51 IO_L25N_N8P3
M0P52 IO_L26P_N8P4
M0P53 IO_L26N_N8P5 Last pin of Nibble 8 in this Bank, Last pin in first Bank of triplet