Recall that any system transaction larger than the DRAM’s basic access unit (typically 64 bytes) is chopped into individual DRAM commands. If addressing is random and transaction size is equal to the DRAM basic access unit, then no address mapping has an advantage. The DRAM controller will reorder transactions to hide page access overhead as much as possible. Expected efficiency is around 40%.
|16R-2B-1BG-7C-1BG-3C||78%||Row-bank-column with bank group optimization|
The ‘Random Block’ addressing is a generalization of random addressing. Once a random address is chosen, an entire block is read linearly. For example, in a badly fragmented virtual address system, linear access in the virtual domain may look like random block addressing in the physical domain, with block size equal to the address translation table.