Read DBI Calibration - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
The DBI pins need to be centered for the same reason as the DQ pins. A small DBI margin affects the validity of the entire byte line.

This is accomplished as follows:

  1. A toggling data pattern is written that will create a 101010 pattern on the DBI pin. Delay the DBI if the toggling pattern is not observed.
  2. After the toggling pattern is detected, continue to shift the DBI until the noise region is found. This establishes the left margin.
  3. Remove the left margin taps, and increment the clock strobe until the noise region is found. This esablishes the right margin.
  4. Revert the clock strobe delays, and compare left and right margins to determine the ideal centering.
There are no debug registers associated with this calibration stage.