Read DQ Per-Bit Deskew and Centering (Simple) - 1.0 English

Calibration Overview

Read Per-Bit DQ Deskew

Because Write Centering calibration has not yet been performed, write operation cannot be carried out properly. Data pattern 10101010 stored in mode register (MPR0) of DRAM is read back to back for performing per bit deskew. The figure shows the pattern read from MPR0 of DRAM.

At the start of deskew, PDQS and NDQS of all the nibbles are delayed together until the PDQS of each nibble finds valid stable region for each bit of its nibble once. Only the rising edge data is checked for correctness. The falling edge comparison is thrown away to allow for extra delay on the PDQS/NDQS relative to the DQ. The final delay tap applied for delaying PDQS and NDQS together is stored as BRAM_RDDQ_QTR_DESKEW_NIBBLE*.

The figure shows the initial alignment of PDQS/NDQS with DQ bits of the nibble.

The figure shows the alignment of PDQS/NDQS with DQ bits of the nibble after detecting valid stable region for all DQ bits in the nibble once.

After detecting valid stable region for all DQ bits in the nibble once. All DQ bits in the nibble are delayed in parallel until valid stable region to noise region crossing is detected on their PDQS sampling. The final DQ IDELAY value from deskew is stored at BRAM_RDDQ_IDELAY_FINAL_BIT*. The figure shows the alignment of PDQS/NDQS with DQ bits in the nibble after detecting transition from valid stable region to noise region.

CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration

The status of Read Per-Bit DQ Deskew can also be determined by decoding the CAL_ERROR result according to the following table.

Read DQS Centering (Simple/MPR)

After the data is deskewed, the PQTR/NQTR delays need to be adjusted to center in the aggregate data valid window for a given nibble. The DRAM MPR register is used to provide the data pattern for centering. Therefore, the pattern changes each bit time and does not rely on being written into the DRAM first, eliminating some uncertainty. Gaps in the reads to the DRAM are used to stress the initial centering to incorporate the effects of ISI on the first DQS pulse as shown in the figure.

Given that the PHY has two capture strobes PDQS/NDQS that need to be centered independently yet moved together, calibration needs to take special care to ensure the clocks stay in a certain phase relationship with one another.

The data and PDQS/NDQS strobe delays start with the value found during DQ per bit deskew. Data is first delayed with IDELAY such that both the PDQS and NDQS clocks start out just to the left of the data valid window for all bits in a given nibble, so the entire read window can be scanned with each clock (see figure below, BRAM_DQ_IDELAY_FINAL_BIT*). Scanning the window with the same delay element and computing the center with that delay element helps to minimize uncertainty in tap resolution that might arise from using different delay lines to find the edges of the read window.

At the start of training, the PDQS/NDQS and data are roughly edge aligned. During deskew the aggregate edge for both PDQS/NDQS is found while you want to find a separate edge for each clock.

After making sure both PDQS/NDQS start outside the data valid region, the clocks are incremented to look for the passing region (see the following figure). Rising edge data is checked for PDQS while falling edge data is checked for NDQS, with a separate check to indicate where the passing region/falling region is for each clock.

When searching for the edge, a minimum window size of 15 is used to guarantee the noise region has been cleared and the true edge is found. The PQDS/NDQS delays are increased past the initial passing point until the minimum window size is found before the left edge is declared as found. If the minimum window is not located across the entire tap range for either clock, an error is asserted.

After the left edge is found (BRAM_RDDQ_PQTR_LEFT_NIBBLE*, BRAM_RDDQ_PQTR_LEFT_NIBBLE*), the right edge of the data valid window can be searched starting from the left edge + minimum window size. Again, the PQTR/NQTR delays are incremented together using step size of 10 taps and checked for error independently to keep track of the right edge of the window. Because the data from the PDQS domain is transferred into the NDQS clock domain in the XPHY, the edge for NDQS is checked first, keeping track of the results for PDQS along the way (see the following figure).

When the NDQS edge is located, a flag is checked to see if the PDQS edge is found as well. If the PDQS edge was not found, the PQTR delay continues to search for the edge, while the NQTR delay stays at its right edge (BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE*, BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE*).

The PQTR/NQTR delays are decremented together using step size of 1 tap to ensure a minimum window size of 15 is detected to guarantee the noise region has been cleared and the true right edge is found (BRAM_RDDQ_PQTR_RIGHT_NIBBLE*, BRAM_RDDQ_NQTR_RIGHT_NIBBLE*).

After both rising and falling edge windows are found, the final center point is calculated based on the left and right edges for each clock. The final delay for each clock (BRAM_RDDQ_PQTR_FINAL_NIBBLE*, BRAM_RDDQ_NQTR_FINAL_NIBBLE*) is computed by: left + ((right – left) / 2).

CAL_ERROR Decode for Read DQS Centering Calibration

The status of Read DQS Centering can also be determined by decoding the CAL_ERROR result according to the following table.