Read DQ Per-Bit Deskew and Centering (Simple) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Each DQ bit is sampled by the internal clock strobe calibrated during the earlier DQS gate stage. The read data is passed through delay elements and are shifted to properly read the data, then the strobes are shifted to center in the data region.

This is accomplished as follows:

  1. Read the pre-written 101010 pattern from the DRAM Mode Register (MR32 and MR40 for LPDDR4, MPR0 for DDR4).
  2. Increment the internal clock coarse taps until the proper data is seen on rising and falling clock edges.
  3. Use the delay elements of all bits in parallel to find the noise region for both the rising and falling edges.
  4. Increment coarse taps to find the noise-to-valid for all bits.
  5. Increment coarse taps until the valid-to-noise region is found for any bit.
  6. Use fine taps to set the rising and falling clocks in the center of the data window.

Table 1. Read DQ Per-Bit Deskew and Centering (Simple) Registers
Register Name Quantity Description
Fx_RDDQ_QTR_DESKEW Nibble Coarse taps needed to find the valid region of rising edge clock
Fx_RDDQ_IDELAY_FINAL DQ bit Final IDELAY values for each data bit in the read path
Fx_RDDQ_PQTR_LEFT Nibble Left edge of valid window for rising edge clock
Fx_RDDQ_NQTR_LEFT Nibble Left edge of valid window for falling edge clock
Fx_RDDQ_PQTR_RIGHT_FCRSE Nibble Valid-to-noise coarse tap value for rising edge clock
Fx_RDDQ_NQTR_RIGHT_FCRSE Nibble Valid-to-noise coarse tap value for falling edge clock
Fx_RDDQ_PQTR_RIGHT Nibble Right edge of valid window for rising edge clock
Fx_RDDQ_NQTR_RIGHT Nibble Right edge of valid window for falling edge clock
Fx_RDDQ_PQTR_FINAL Nibble Final delay value for rising edge clock strobe
Fx_RDDQ_NQTR_FINAL Nibble Final delay value for falling edge clock strobe