Read DQS Centering (Complex) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

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1.0 English
Note: This calibration stage is skipped for data rates at or below 2,133 Mbps. At these data rates, the data eye is wide enough that prior calibration stages provide adequate DQS centering.
The final stage of DQS read centering that is completed before normal operation is repeating the steps performed during MPR DQS read centering but with a more difficult/complex pattern. The purpose of using a complex pattern is to stress the system for SI effects such as ISI and noise while calculating the read DQS center position. This ensures that the read center position can reliably capture data with margin in a true system.