If the Read DBI option is selected for DDR4/LPDDR4/4X, the position of the DQS in the data valid window must also use the timing information of the DBI pin itself, because the DBI pin can be the limit to the data valid window.
0F0F0F0F pattern is written to the DRAM and
read back with read DBI enabled. The DRAM sends the data back as
FFFFFFFF but the DBI pin has the clock pattern
01010101, which is used to measure the data valid window of the DBI input
pin itself. The final DQS location is determined based on the aggregate window for the
DQ and DBI pins.