Read Per-Bit Deskew - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Read Per-Bit deskew is performed on a per-bit basis whereas Read DQS centering is performed on a per-nibble basis. During per-bit deskew, a predefined training pattern of 101010... is read back from the DRAM while DQS adjustments (PQTR and NQTR individual fine taps on DQS) and DQ adjustments (IDELAY) are made. At the end of this stage, the DQ bits are internally deskewed to the left edge of the incoming DQS.