Reordering - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The Memory Controller utilizes a state machine to determine reordering priority. Depending on the state of the transactions, it will either optimize for efficiency (reordering to take advantage of open pages) or it may service transactions which have been left idle for too long.

There are four states: Read Priority, Write Priority, Write/Read, and Starved.

Read Priority
Read transactions are given priority by allowing Read page miss transactions to execute a precharge even when there is a pending write to the same bank. Write transactions cannot execute a precharge if there is a pending read page hit. This is the default state.
Write Priority
The number of write commands have exceeded a threshold and so writes will take priority until the pressure is lowered.
Write/Read
Efficient transactions are the priority in this state. Reordering commands for page hits are prioritized.
Starved
One or more read transactions are starved and only starved Reads and any Writes coincident with starved Reads are selected.

VC1902, VC1802, and VM1802 devices have a single read reordering buffer in each memory controller. When a memory controller is configured in dual-channel mode, half of the buffer is assigned to each channel. This reduced buffer depth will result in efficiency loss for read operations because of the reduced reordering flexibility. The amount is dependent on the address pattern of the reads.

All other Versal devices have two read reordering buffers in each memory controller, yielding better read efficiency in both single- and dual-channel mode. See Versal Devices with Dual Read Reorder Buffers for more information.