Revision History - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The following table shows the revision history for this document.

Section Revision Summary
12/14/2022 Version 1.0
General Updates
  • Updated for HBM support
  • Updated for NMU Address Re-mapping
04/27/2022 Version 1.0
General Updates
  • Added new sys_clk options.
  • Added M:N AXI4-Stream support.
  • Added description of dual read reorder buffer devices.
  • Clarified ECC and non-ECC pinouts.
  • Updated Designing with the Core to match latest GUI options.
  • Added DDRMC Migration section.
11/08/2021 Version 1.0
General Updates Updates for release 2021.2.
Data Poisoning New section.
Periodic Reads New section.
XPLL New section.
System Address Map Section title change.
UART Debug New section.
08/12/2021 Version 1.0
NoC Architecture
  • Added AXI Conversion Section
  • General updates for clarification. Restructured the section to split out NoC and DDRMC Architectures.
NoC and Memory Controller Simulation Added Simulation content.
04/08/2021 Version 1.0
NoC Architecture General updates/clarifications.
Versal Programmable Network on Chip Overview
  • Rewrite for clarification
  • Updated NoC Functions
NoC and Memory Controller Simulation New Chapter.
General updates Restructuring for improved coherency.
11/23/2020 Version 1.0
DDR Memory Controller
Memory Interface Debug Added: DDRMC Calibration Debug
Customizing and Generating the Core Added information on Interrupt and Parity options.
07/16/2020 Version 1.0
Initial release N/A