Revision History - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2023-11-01

Version

1.0 English

The following table shows the revision history for this document.

Section	Revision Summary
11/01/2023 Version 1.0
Overview	Added link to the HBM GitHub tutorials.
NoC Architecture	Added Multi-SLR NoC Boot Paths Updated NoC Components Updated NoC Communication Updated parity support for HBM.
Integrated Memory Controller (DDRMC) Architecture	Added Decoding DDRMC ECC Errors. Updated Refresh Updated XPLL
Integrated HBM Controller	Updated Core Architecture Updated clocking section. Updated HBM Stack Temperature. Added new section for Error Reporting and Monitoring.
Designing with the Core	Updated new section for Configuring the HBM PHYIO Control IP. Updated Configuring the HBM Controller. Updated latest GUI figures.
NoC and Memory Controller Simulation	Added the link to HBM GitHub tutorials.
NoC Performance Tuning	Updated Address Mapping section for HBM. Added a new section for AXI considerations under HBM System Considerations. Updated Single ID Versus Multiple ID for AXI Transactions under HBM System Considerations. Updated HBM2E Access LatencyHBM2E Access Latencies section.
System Address Map	Updated System Address Map table.
Memory Interface Debug	Updated Memory Debug: Tcl Usage.
05/16/2023 Version 1.0
General updates	Updated for 2023.1 Updated Integrated HBM Controller. Changed title to 'Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller.’
Calibration Stages	Updated for 2023.1
NoC Architecture	Added sections on HBM_NMU, HBM_NSU, and NoC 8x8 Switch.
Designing with the Core	Updated the AXI NoC IP sections for HBM.
NoC Performance Tuning	Added content for HBM System Consideration.
12/14/2022 Version 1.0
General Updates	Updated for HBM support Updated for NMU Address Re-mapping
04/27/2022 Version 1.0
General Updates	Added new sys_clk options. Added M:N AXI4-Stream support. Added description of dual read reorder buffer devices. Clarified ECC and non-ECC pinouts. Updated Designing with the Core to match latest GUI options. Added DDRMC Migration section.
11/08/2021 Version 1.0
General Updates	Updates for release 2021.2.
Data Poisoning	New section.
Periodic Reads	New section.
XPLL	New section.
System Address Map	Section title change.
UART Debug	New section.
08/12/2021 Version 1.0
NoC Architecture	Added AXI Conversion Section General updates for clarification. Restructured the section to split out NoC and DDRMC Architectures.
NoC and Memory Controller Simulation	Added Simulation content.
04/08/2021 Version 1.0
NoC Architecture	General updates/clarifications.
Versal Programmable NoC Overview	Rewrite for clarification Updated NoC Functions
NoC and Memory Controller Simulation	New Chapter.
General updates	Restructuring for improved coherency.
11/23/2020 Version 1.0
DDR Memory Controller	Updated Design Generation Flow for 2020.2 release. Updated: Pinout Rules Added: Pinout Options for Future Expansion
Memory Interface Debug	Added: DDRMC Calibration Debug
Customizing and Generating the Core	Added information on Interrupt and Parity options.
07/16/2020 Version 1.0
Initial release	N/A