The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
12/14/2022 Version 1.0 | |
General Updates |
|
04/27/2022 Version 1.0 | |
General Updates |
|
11/08/2021 Version 1.0 | |
General Updates | Updates for release 2021.2. |
Data Poisoning | New section. |
Periodic Reads | New section. |
XPLL | New section. |
System Address Map | Section title change. |
UART Debug | New section. |
08/12/2021 Version 1.0 | |
NoC Architecture |
|
NoC and Memory Controller Simulation | Added Simulation content. |
04/08/2021 Version 1.0 | |
NoC Architecture | General updates/clarifications. |
Versal Programmable Network on Chip Overview |
|
NoC and Memory Controller Simulation | New Chapter. |
General updates | Restructuring for improved coherency. |
11/23/2020 Version 1.0 | |
DDR Memory Controller |
|
Memory Interface Debug | Added: DDRMC Calibration Debug |
Customizing and Generating the Core | Added information on Interrupt and Parity options. |
07/16/2020 Version 1.0 | |
Initial release | N/A |