When a read transaction size is smaller than the access quantum of the DRAM, bandwidth is always wasted. For example, a 32-byte read request to a 1x64 DDR4 DRAM, will always read 64 bytes and discard half the data, imposing a 50% efficiency reduction on top of the normal DRAM efficiency.
When a write transaction size is smaller than the access quantum of the DRAM, two possibilities exist. The first is behavior similar to the read case where 50% of the efficiency is lost. The second possibility is that while the transaction is pending in the queue, a subsequent transaction to the next address will merge with the current transaction to make it a whole access quantum, thereby losing no efficiency. This behavior is attributed to the “write combine” feature of the DDRMC. Thus, linear access writes will be efficient even when using 32B access in a 1x64 configuration, but random access writes will not.