Single Channel Component Interfaces - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The minimum Single Channel DDR4 Component interface configuration is 16-bits while the maximum is 72-bits with ECC. For most configurations there will be two pinout options; either Optimum or CLK Expansion. CLK Expansion is only required for DDP Deep applications with five or more devices. If the DDRMC configuration already has two DDR4 output clocks enabled then the only pinout option will be Optimum. When planning for future memory topology expansions the maximum configuration will depend on whether DDP Deep devices are required. If they are not required then a single rank 72-bit interface with the appropriate 3DS, ECC, Command/Address Parity, DM/DBI, and Pinout Swapping options will allow for DQ width, 3DS device support, and ECC expansion when selecting the Optimum pinout option. If the future topology requires DDP Deep devices then the maximum pinout must be generated with a Dual Rank configuration to ensure the additional Control signals are included in the pinout. If CLK expansion is required then generate the pinout as Dual Rank with two DDR4 output clocks enabled if it is not already enabled in the tools. DDP Deep 3DS Component interfaces are not supported. JEDEC standards include compatibility for DDP Deep and 3DS based packages with a single hardware design so it is possible to generate a single pinout compatible with either type of device.