Single Channel DDR4 Component Interfaces - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Available options in single channel topology:

  • Single Channel 16-bit
  • Single Channel 24-bit as 16-bit Data with 8-bit ECC
  • Single Channel 32-bit
  • Single Channel 40-bit as 32-bit Data with 8-bit ECC
  • Single Channel 64-bit
  • Single Channel 72-bit as 64-bit Data with 8-bit ECC

PCB Expansion Options:

  • Optimum
  • CLK Expansion

For Single Channel DDR4 Component interfaces there are two distinct pinouts. The first is Optimum which efficiently packs the Triplet based on the data width. The other is CLK Expansion which is fundamentally a different pinout than the Optimum with two DDR4 CLK outputs generated for DDP Deep topologies. For most applications the Optimum pinout is acceptable and will allow for future expansion if adding ECC, 3DS devices, or expanding the data width. The CLK Expansion option is only required when migrating to DDP Deep devices in the future. The current Versal DDR4 solution only supports x8 DDP Deep devices and two DDR4 CLK outputs are only required when five or more components are present as with data widths of 40-bits, 64-bits, or 72-bits. It is not possible to generate any other Single Channel topology which requires two CLK outputs at this time. The logical ranks found in 3DS devices do not add additional loading like DDP Deep devices so there is no need for CLK expansion with these components. There is no support for DDP Deep 3DS Single Channel or Dual Channel component interfaces. DDP Deep 3DS components are supported in RDIMM/LRDIMM applications.

The Optimum single clock output pinout leaves free Nibbles open on the far Right Bank, and depending on your data width, more Nibbles will be available moving Right to Left. The CLK Expansion pinout has two free Nibbles, one in the first Bank and one in the last Bank. The CLK Expansion pinout will have more free Nibbles starting in the Right bank and moving Left as your data width decreases. Both pinouts support 3DS and Rank expansion, but the CLK Expansion pinout must be used for DDP Deep devices with five or more placements. If the DDRMC configuration already has two CLKs enabled then the only pinout option will be Optimum which is the CLK Expansion pinout.
Figure 1. Single Channel up to 72-Bit DDR4 Component Pinout with Single DDR4 Clock Output
Figure 2. CLK Expansion Single Channel up to 72-Bit DDR4 Component Pinout with Two DDR4 Clocks