Single Channel LPDDR4/4X Interfaces - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Available options in single channel topology:

  • Single Channel 16-bit
  • Single Channel 32-bit
  • Single Channel 32-bit as 16-bit Data with 16-bit ECC
  • Single Channel 48-bit as 32-bit Data with 16-bit ECC

PCB Expansion Options:

  • Optimum

All Single Channel LPDDR4/4X interfaces will always give the Optimum option. This is because all configurations follow the same basic pinout while more Nibbles are used as the data width increases. As the data width expands from 16-bits to 32-bits or 32-bits to 48-bits additional Address/Command signals are generated for the additional LPDDR4/4X data channel. The Optimum pinout supports single or dual rank topologies. It is also possible for Single Channel interfaces to expand to Dual Channel interfaces. This is because the non-pin efficient Dual Channel 32-bit pinout is compatible with the individual LPDDR4/4X data channels along with their respective Command/Address bus. All Single Channel LPDDR4/4X interfaces will not be able to select the LP4 Pin Efficient option in the GUI. This ensures forward compatibility with other topologies.

Figure 1. Single Channel 16-bit (1x16) LPDDR4/4X Interface Pinout
Figure 2. Single Channel 32-bit LPDDR4/4X Interface Pinout
Figure 3. Single Channel 48-bit LPDDR4/4X Interface Pinout with DQA2 and ACA2 being the ECC Channel