Simple AXI masters use a single AXI ID for all issued transactions. As a result, in adherence to AXI ordering rules, transaction responses must be returned in the order issued. This ordering requirement could in some cases adversely affect performance. The alternative is for the AXI master to issue each transaction with a different AXI ID and accept responses in any arrival order. This is explained in detail in the following sections:
The performance of the read transactions are not affected by the use of a Single AXI ID versus Multiple AXI ID. The NMUs apply a unique ID to each read transaction regardless of the originator's AXI ID. The NMUs contain a reorder buffer (RROB) that can accept returned data from all issued transactions, and it ensures the responses are returned in the correct order. The HBM_NMUs have an increased RROB size which can hold up to 64 entries of 64 bytes per entry.
The performance of the write transactions are impacted when using a Single AXI ID. This is because the NMU does not apply an unique ID to write transactions. Thus, in cases of UNR traffic where a master is accessing multiple destinations, it is subjected to the SSID effect. The HBM_NMUs support different write ordering methods, as described in Write Ordering.