A single device accesses the entire memory linearly. Access within a page (row) is very efficient, but switching pages can cause loss of efficiency. To minimize the loss, choose a mapping that will switch banks at page boundaries and, furthermore, alternate between different bank groups after each 64-byte DRAM command.
The chosen mapping is therefore: 16R-2B-1BG-7C-1BG-3C.
This mapping places a bank group bit after three column bits. This ensures that back-to-back DRAM commands target different bank groups and avoid same-group penalty. For comparison, the following table shows performance with other possible mappings.
|16R-2B-1BG-7C-1BG-3C||95%||Row-bank-column with bank group optimization|