Single x64 vs. Dual x32 DDR4 Configuration - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

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The DDRMC can be configured in Single- or Dual-Channel mode. For a 64-bit DDR4 interface, this means the controller can support a single x64 channel, or dual x32 channels. This selection is made on the DDR Memory tab of the AXI NoC configuration dialog. This choice affects performance as follows.
Table 1. Single- vs. Dual-Channel Trade-offs
Feature 1 x64 2 x32 Notes
Storage - - Same
Access Quantum 64 bytes 32 bytes For some 32-byte use cases, 2 x32 can be significantly more efficient.
Read efficiency (VC1902, VC1802, and VM1802) Good Fair Both channels share the same read reorder buffer in these devices, causing some performance limitations.
Read efficiency (Other devices) Good Good Dual read reorder buffers allow more reordering of transactions
Write efficiency Good Good Shared resources cause some performance loss.

Likewise, an LPDDR4 controller can support a single 1x32 channel, or a dual 2x32 channel.

The next few figures show examples of read and write efficiency differences between single and dual-channels for random and linear addressing. All the data shown is for DDR4 at 3200 Mb/s or LPDDR4 at 4267 MB/s. These figures are applicable for VC1902, VC1802, and VM1802 devices only.

Important: Actual efficiency may differ from the values illustrated below depending on traffic type, address mapping, data rate, and other variables.

The following figure illustrates efficiency differences for DDR4 random reads. Single-channel efficiency is shown in black, while corresponding dual-channel efficiency is shown in gray. The shared read reorder buffer causes a decrease in efficiency for dual-channel compared to single-channel.

Figure 1. DDR4 Random Read Efficiency (VC1902, VC1802, and VM1802)

By contrast, the following figure illustrates that for DDR4 random writes, there is only a small efficiency difference between dual-channel and single-channel operation.

Figure 2. DDR4 Random Write Efficiency (VC1902, VC1802, and VM1802)

Similarly, for LPDDR4 the random read efficiency is impacted by the shared read reorder buffer, while random write efficiency is not significantly affected. This is illustrated in the following two figures.

Figure 3. LPDDR4 Random Read Efficiency (VC1902, VC1802, and VM1802)
Figure 4. LPDDR4 Random Write Efficiency (VC1902, VC1802, and VM1802)

Linear read traffic also shows some efficiency degradation for DDR4 dual-channel operation. This efficiency loss is less pronounced for LPDDR4. The following figure illustrates some sample efficiencies for DDR4 and LPDDR4 linear read traffic.

Figure 5. Linear Read Efficiency (VC1902, VC1802, and VM1802)