|For some 32-byte use cases, 2 x32 can be significantly more efficient.
|Read efficiency (VC1902, VC1802, and VM1802)
|Both channels share the same read reorder buffer in these devices, causing some performance limitations.
|Read efficiency (Other devices)
|Dual read reorder buffers allow more reordering of transactions
|Shared resources cause some performance loss.
Likewise, an LPDDR4 controller can support a single 1x32 channel, or a dual 2x32 channel.
The next few figures show examples of read and write efficiency differences between single and dual-channels for random and linear addressing. All the data shown is for DDR4 at 3200 Mb/s or LPDDR4 at 4267 MB/s. These figures are applicable for VC1902, VC1802, and VM1802 devices only.
The following figure illustrates efficiency differences for DDR4 random reads. Single-channel efficiency is shown in black, while corresponding dual-channel efficiency is shown in gray. The shared read reorder buffer causes a decrease in efficiency for dual-channel compared to single-channel.
By contrast, the following figure illustrates that for DDR4 random writes, there is only a small efficiency difference between dual-channel and single-channel operation.
Similarly, for LPDDR4 the random read efficiency is impacted by the shared read reorder buffer, while random write efficiency is not significantly affected. This is illustrated in the following two figures.
Linear read traffic also shows some efficiency degradation for DDR4 dual-channel operation. This efficiency loss is less pronounced for LPDDR4. The following figure illustrates some sample efficiencies for DDR4 and LPDDR4 linear read traffic.