The noc_sim_wrapper - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

When netlisting for rtl simulation the constructed model is split across different components of the design. The NoC endpoints (for example NMUs, NSUs, DDRMCs) are instantiated in the containing axi_noc and axis_noc instances, while a new block called "xlnoc" is constructed to contain the set of connection components (for example NPSs, NIDBs) required to implement the NoC routing solution.

Vivado creates a new top-level wrapper file called <design>_wrapper_sim_wrapper.v to stitch the xlnoc block into the simulation netlist. The original <design>_wrapper is not modified but is instantiated in the new top-level along with a single instance of the constructed xlnoc. <design>_wrapper_sim_wrapper connects the ports of xlnoc to the corresponding NoC endpoint ports by reaching into the design hierarchy using Verilog hierarchical references.

The file <design>_wrapper_sim_wrapper.v is constructed in the project sources directory by the launch_simulation command. The Simulation top module name on the Simulation Settings page will be set to <design>_wrapper_sim_wrapper. To create the wrapper file without invoking the Vivado simulator specify the -scripts_only option to launch_simulation.

Another method to generate the xlnoc and the file <design>_wrapper_sim_wrapper.v is to use the generate_switch_network_for_noc TCL command. This command is recommended for scripted simulation flows outside of Vivado.