UART Debug - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

In the event of calibration failure, the recommended debug method is to use the Hardware Manager to view the calibration status. When this is not possible, there is information provided in the UART0 output (enabled via CIPS). The output looks similar to the following:

[timestamp] ====DDRMC Register Dump Start======
[timestamp] DDRMC_0 (UB 0xF6110000)
[timestamp] PCSR Control: 0x3
[timestamp] PCSR Status: 0x27
[timestamp] Calibration Error: 0xE
[timestamp] Nibble Location 1: 0x0
[timestamp] Nibble Location 2: 0xA
[timestamp] Nibble Location 3: 0x0
[timestamp] Calibration Stage: 0x1CB

Depending on the Versal device, the number of DDRMC_x reported will vary. There will be one set of data per DDRMC instance.

DDRMC_x
This defines the DDRMC instance and the base register information for the DDRMC_UB_x block.
PCSR Control
The only relevant bit is bit 0. A value of b1 indicates that the Memory Controller is enabled in the design.
PCSR Status
Table 1. Bit Field Descriptions
Bit Field Description
5 CALERROR : 1 if there is an error during calibration
4 CALDONE : 1 if calibration has completed
3 INCAL : 1 if calibration is still in progress

Calibration Error

Convert the hex code to decimal, and refer to the following table.
Table 2. Calibration Error Codes
CODE ERROR
0 No error code generated
1 XPLL Timeout waiting for lock
2 XPLL found calibration error
3 XPHY BISC timeout waiting for BISC fixdly rdy
4 XPHY BISC found rl dly qtr value to be 0
5 MEM INIT timeout waiting for memory initialization to complete
6 DQS gating timeout waiting for XPHY gate training to complete
7 DQS gating reached maximum read latency limit
8 DQS gating found rank to rank skew greater than expected
9 Write leveling failed to find rising edge using coarse and fine offsets
10 Write leveling failed in stable 0 confirmation stage
11 Write leveling reached maximum taps to find noise width by incrementing DQS odelay
12 Read DQ failed to find rising edge valid window by incrementing PQTR
13 Read DQ failed to find rising edge valid window by incrementing DQ idelay
14 Read DQ failed to find rising edge noise region by incrementing DQ idelay by higher taps
15 Read DQ failed to find rising edge noise region by incrementing DQ idelay
16 Read DQ failed to find noise region by incrementing DQ idelay
17 Read DQ failed to find left edge by incrementing PQTR and NQTR
18 Read DQ failed to find right edge by decrementing PQTR and NQTR
19 Read DQ failed in negative test post sanity check
20 Read DQ failed in positive test post sanity check
21 Write DQ-DBI failed to find valid window by moving DQS odelay first and then DQ odelay
22 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DQ odelay by higher taps
23 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DQ odelay
24 Write DQ-DBI failed to find valid window by moving DQS odelay first and then DBI odelay
25 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DBI odelay by higher taps
26 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DBI odelay
27 Write DQ-DBI failed to find the right edge by incrementing DQS odelay by higher taps
28 Write DQ-DBI failed to find the right edge by incrementing DQS odelay
29 Write DQ-DBI failed in post sanity check
30 Write DQ-DBI failed to find the valid window by incrementing DQ odelay
31 Write DQ-DBI doesn't have enough taps to decrement DQ odelay
32 Write DQ-DBI failed to find the valid window by incrementing DBI odelay
33 Write DQ-DBI failed to find the left edge by incrementing DQ odelay by higher taps
34 Write DQ-DBI failed to find the left edge by incrementing DQ odelay
35 Write DQ-DBI read DQS oscillator value to be 0
36 Write DQ-DBI computed tDQS2DQ value to be out of range
37 Write latency failed to find expected data pattern
38 Write latency found larger rank to rank skews than is supported
39 Write latency failed in post sanity check
40 Write latency failed in sanity check 1
41 Write latency failed in sanity check 2
42 Write latency failed in read complex pattern sanity check
43 Write latency failed in write complex pattern sanity check
44 Write latency failed in PRBS read pattern sanity check
45 Write latency failed in PRBS write pattern sanity check
46 Write latency read DQS oscillator value unexpectedly found to be 0
47 Write latency computed tDQS2DQ value to be out of range
48 Read DBI failed to find valid window by incrementing DBI idelay
49 Read complex failed to find noise region by incrementing DQ idelay
50 Read complex failed to find left edge by incrementing PQTR and NQTR using short complex burst
51 Read complex failed to find left edge by incrementing PQTR and NQTR
52 Read complex failed to find right edge by decrementing PQTR and NQTR using short compex burst
53 Read complex failed to find right edge by decrementing PQTR and NQTR
54 Read complex failed in positive test post sanity check
55 Write complex failed to find the left edge by incrementing DQ odelay by higher taps
56 Write complex failed to find the left edge by incrementing DQ odelay
57 Write complex failed to find the right edge by incrementing DQS odelay by higher taps
58 Write complex failed to find the right edge by incrementing DQS odelay
59 Write complex failed in post sanity check
60 Write complex failed to find the right edge by decrementing DQ odelay by higher taps
61 Write complex failed to find the right edge by decrementing DQ odelay
62 Write complex failed in post sanity check 1
63 Write complex read DQS oscillator value unexpectedly found to be 0
64 Write complex computed tDQS2DQ value to be out of range
65 Read PRBS failed in pre sanity check
66 Read PRBS failed to find left edge by incrementing PQTR and NQTR
67 Read PRBS failed to find right edge by decrementing PQTR and NQTR
68 Read PRBS failed in positive test post sanity check
69 Write PRBS failed to find left margin by incrementing DQ odelays by higher taps
70 Write PRBS failed to find left margin by incrementing DQ odelays
71 Write PRBS failed to find right margin by incrementing DQS odelays by higher taps
72 Write PRBS failed to find right margin by incrementing DQS odelays
73 Write PRBS failed to find right margin by decrementing DQ odelays by higher taps
74 Write PRBS failed to find right margin by decrementing DQ odelays
75 Write PRBS failed in post sanity check 1
76 Calibration enable VTC failed in post sanity check 1
77 Calibration read DQS tracking failed in post sanity check 1
78 Calibration read DQS tracking found RLDLYRNK coarse underflow
79 Calibration read DQS tracking found RLDLYRNK coarse overflow
80 Calibration LP4 oscillator tracking failed in pre sanity check 1
81 Calibration LP4 oscillator tracking failed in sanity check 1
82 Calibration LP4 oscillator tracking failed in post sanity check 1
83 Calibration LP4 oscillator tracking read DQS oscillator value to be 0
84 Calibration LP4 oscillator tracking computed tDQS2DQ value to be out of range
85 Read DQS gate tracking found RLDLYRNK coarse underflow
86 Read DQS gate tracking found RLDLYRNK coarse overflow
87 LP4 oscillator tracking read DQS oscillator value to be 0
88 LP4 oscillator tracking computed tDQS2DQ value to be out of range
89 LP4 oscillator tracking rank switching did not take effect
90 Self refresh exit DQS gating timeout waiting for XPHY gate training done signal
91 Self refresh exit DQS gating reached maximum read latency limit
92 Self refresh exit DQS gating found rank to rank skew greater than expected
93 Self refresh exit read DQS tracking failed in sanity check ddr
94 Self refresh exit read DQS tracking found RLDLYRNK coarse underflow
95 Self refresh exit read DQS tracking found RLDLYRNK coarse overflow
96 Frequency switching waiting for BISC pause ready signal
97 Frequency switching timeout waiting for XPLL lock signal
98 Frequency switching XPLL found calibration error
99 Frequency switching timeout waiting for BISC fixdly rdy signal
100 Frequency switching found zero rl dly qtr value after XPHY BISC
101 Frequency switching failed in enable VTC post sanity check 1
102 Parity error occurred during transaction re-transmission
103 Watchdog timeout while polling scrub busy after scrub being stopped
104 Watchdog timeout while polling scrub busy after scrub being enabled
105 Watchdog timeout while polling self refresh entry request from DC FSM
106 Watchdog timeout while polling self refresh exit request from DC FSM
107 Watchdog timeout while polling self refresh exit done from DC FSM
108 Calibration enable VTC timeout waiting for phy_rdy
109 Frequency switching enable VTC timeout waiting for phy_rdy
110 Restore calibration timeout waiting for XPLL lock signal
111 Restore calibration XPLL found calibration error
112 Restore calibration timeout waiting for BISC fixdly rdy signal
113 Restore calibration found zero rl dly qtr value after XPHY BISC
114 Restore calibration failed in enable VTC post sanity check 1
115 Restore calibration enable VTC timeout waiting for phy_rdy
116 CA calibration failed to find noise right edge while incrementing CA odelay by higher taps
117 CA calibration failed to find noise right edge while incrementing CA odelay
118 CA calibration failed in CA odelay centering stage
119 CA calibration failed to find noise right edge while incrementing CS odelay by higher taps
120 CA calibration failed to find noise right edge while incrementing CS odelay
121 CA calibration failed in CS odelay centering stage
122 Write DQ-DBI calibration failed to find right edge deep noise by incrementing DQ odelay
123 Write DQ-DBI calibration failed to find right edge deep noise by incrementing DBI odelay
124 Write DQ-DBI calibration failed to find right edge valid window by incrementing DBI odelay
125 Write DQ-DBI calibration failed to find right edge low noise by decrementing DBI odelay
126 Write DQ-DBI calibration failed to find right edge valid window by incrementing DQ odelay
127 Write DQ-DBI calibration failed to find right edge low noise by decrementing DQ odelay

Nibble location 1,2,3:

These three fields each contain nine bits of data. One bit for each nibble in an IO bank in the given triplet. Nibble location 3 [8:0] for the third IO bank. Nibble location 2 [8:0] for the second IO bank, and Nibble location 1 [8:0] for the first IO bank. A ‘1’ in any of these bit locations represents the nibble where a failure was detected associated with the error code defined earlier. Some calibration stages are done in parallel, so it is possible for multiple nibbles to be flagged.

Calibration Status/Stage:

This hex code represents nine bits of data.

See Table 1 for information on the contents.