UART Debug - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2023-11-01
Version
1.0 English

In the event of calibration failure, the recommended debug method is to use the Hardware Manager to view the calibration status. When this is not possible, there is information provided in the UART0 output (enabled via CIPS). The output looks similar to the following:

[timestamp] ====DDRMC Register Dump Start======
[timestamp] DDRMC_0 (UB 0xF6110000)
[timestamp] PCSR Control: 0x3
[timestamp] PCSR Status: 0x27
[timestamp] Calibration Error: 0xE
[timestamp] Nibble Location 1: 0x0
[timestamp] Nibble Location 2: 0xA
[timestamp] Nibble Location 3: 0x0
[timestamp] Calibration Stage: 0x1CB

Depending on the Versal device, the number of DDRMC_x reported will vary. There will be one set of data per DDRMC instance.

DDRMC_x
This defines the DDRMC instance and the base register information for the DDRMC_UB_x block.
PCSR Control
The only relevant bit is bit 0. A value of b1 indicates that the Memory Controller is enabled in the design.
PCSR Status
Table 1. Bit Field Descriptions
Bit Field Description
5 CALERROR : 1 if there is an error during calibration
4 CALDONE : 1 if calibration has completed
3 INCAL : 1 if calibration is still in progress

Calibration Error

Refer to the following table.

Table 2. Calibration Error Codes
CODE ERROR
0x0 No error code generated
0x1 XPLL Timeout waiting for lock
0x2 XPLL found calibration error
0x3 XPHY BISC timeout waiting for BISC fixdly rdy
0x4 XPHY BISC found rl dly qtr value to be 0
0x5 MEM INIT timeout waiting for memory initialization to complete
0x6 DQS gating timeout waiting for XPHY gate training to complete
0x7 DQS gating reached maximum read latency limit
0x8 DQS gating found rank to rank skew greater than expected
0x9 Write leveling failed to find rising edge using coarse and fine offsets
0xA Write leveling failed in stable 0 confirmation stage
0xB Write leveling reached maximum taps to find noise width by incrementing DQS odelay
0xC Read DQ failed to find rising edge valid window by incrementing PQTR
0xD Read DQ failed to find rising edge valid window by incrementing DQ idelay
0xE Read DQ failed to find rising edge noise region by incrementing DQ idelay by higher taps
0xF Read DQ failed to find rising edge noise region by incrementing DQ idelay
0x10 Read DQ failed to find noise region by incrementing DQ idelay
0x11 Read DQ failed to find left edge by incrementing PQTR and NQTR
0x12 Read DQ failed to find right edge by decrementing PQTR and NQTR
0x13 Read DQ failed in negative test post sanity check
0x14 Read DQ failed in positive test post sanity check
0x15 Write DQ-DBI failed to find valid window by moving DQS odelay first and then DQ odelay
0x16 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DQ odelay by higher taps
0x17 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DQ odelay
0x18 Write DQ-DBI failed to find valid window by moving DQS odelay first and then DBI odelay
0x19 Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DBI odelay by higher taps
0x1A Write DQ-DBI failed to find the noise region for per-bit deskew by incrementing DBI odelay
0x1B Write DQ-DBI failed to find the right edge by incrementing DQS odelay by higher taps
0x1C Write DQ-DBI failed to find the right edge by incrementing DQS odelay
0x1D Write DQ-DBI failed in post sanity check
0x1E Write DQ-DBI failed to find the valid window by incrementing DQ odelay
0x1F Write DQ-DBI doesn't have enough taps to decrement DQ odelay
0x20 Write DQ-DBI failed to find the valid window by incrementing DBI odelay
0x21 Write DQ-DBI failed to find the left edge by incrementing DQ odelay by higher taps
0x22 Write DQ-DBI failed to find the left edge by incrementing DQ odelay
0x23 Write DQ-DBI read DQS oscillator value to be 0
0x24 Write DQ-DBI computed tDQS2DQ value to be out of range
0x25 Write latency failed to find expected data pattern
0x26 Write latency found larger rank to rank skews than is supported
0x27 Write latency failed in post sanity check
0x28 Write latency failed in sanity check 1
0x29 Write latency failed in sanity check 2
0x2A Write latency failed in read complex pattern sanity check
0x2B Write latency failed in write complex pattern sanity check
0x2C Write latency failed in PRBS read pattern sanity check
0x2D Write latency failed in PRBS write pattern sanity check
0x2E Write latency read DQS oscillator value unexpectedly found to be 0
0x2F Write latency computed tDQS2DQ value to be out of range
0x30 Read DBI failed to find valid window by incrementing DBI idelay
0x31 Read complex failed to find noise region by incrementing DQ idelay
0x32 Read complex failed to find left edge by incrementing PQTR and NQTR using short complex burst
0x33 Read complex failed to find left edge by incrementing PQTR and NQTR
0x34 Read complex failed to find right edge by decrementing PQTR and NQTR using short compex burst
0x35 Read complex failed to find right edge by decrementing PQTR and NQTR
0x36 Read complex failed in positive test post sanity check
0x37 Write complex failed to find the left edge by incrementing DQ odelay by higher taps
0x38 Write complex failed to find the left edge by incrementing DQ odelay
0x39 Write complex failed to find the right edge by incrementing DQS odelay by higher taps
0x3A Write complex failed to find the right edge by incrementing DQS odelay
0x3B Write complex failed in post sanity check
0x3C Write complex failed to find the right edge by decrementing DQ odelay by higher taps
0x3D Write complex failed to find the right edge by decrementing DQ odelay
0x3E Write complex failed in post sanity check 1
0x3F Write complex read DQS oscillator value unexpectedly found to be 0
0x40 Write complex computed tDQS2DQ value to be out of range
0x41 Read PRBS failed in pre sanity check
0x42 Read PRBS failed to find left edge by incrementing PQTR and NQTR
0x43 Read PRBS failed to find right edge by decrementing PQTR and NQTR
0x44 Read PRBS failed in positive test post sanity check
0x45 Write PRBS failed to find left margin by incrementing DQ odelays by higher taps
0x46 Write PRBS failed to find left margin by incrementing DQ odelays
0x47 Write PRBS failed to find right margin by incrementing DQS odelays by higher taps
0x48 Write PRBS failed to find right margin by incrementing DQS odelays
0x49 Write PRBS failed to find right margin by decrementing DQ odelays by higher taps
0x4A Write PRBS failed to find right margin by decrementing DQ odelays
0x4B Write PRBS failed in post sanity check 1
0x4C Calibration enable VTC failed in post sanity check 1
0x4D Calibration read DQS tracking failed in post sanity check 1
0x4E Calibration read DQS tracking found RLDLYRNK coarse underflow
0x4F Calibration read DQS tracking found RLDLYRNK coarse overflow
0x50 Calibration LP4 oscillator tracking failed in pre sanity check 1
0x51 Calibration LP4 oscillator tracking failed in sanity check 1
0x52 Calibration LP4 oscillator tracking failed in post sanity check 1
0x53 Calibration LP4 oscillator tracking read DQS oscillator value to be 0
0x54 Calibration LP4 oscillator tracking computed tDQS2DQ value to be out of range
0x55 Read DQS gate tracking found RLDLYRNK coarse underflow
0x56 Read DQS gate tracking found RLDLYRNK coarse overflow
0x57 LP4 oscillator tracking read DQS oscillator value to be 0
0x58 LP4 oscillator tracking computed tDQS2DQ value to be out of range
0x59 LP4 oscillator tracking rank switching did not take effect
0x5A Self refresh exit DQS gating timeout waiting for XPHY gate training done signal
0x5B Self refresh exit DQS gating reached maximum read latency limit
0x5C Self refresh exit DQS gating found rank to rank skew greater than expected
0x5D Self refresh exit read DQS tracking failed in sanity check ddr
0x5E Self refresh exit read DQS tracking found RLDLYRNK coarse underflow
0x5F Self refresh exit read DQS tracking found RLDLYRNK coarse overflow
0x60 Frequency switching waiting for BISC pause ready signal
0x61 Frequency switching timeout waiting for XPLL lock signal
0x62 Frequency switching XPLL found calibration error
0x63 Frequency switching timeout waiting for BISC fixdly rdy signal
0x64 Frequency switching found zero rl dly qtr value after XPHY BISC
0x65 Frequency switching failed in enable VTC post sanity check 1
0x66 Parity error occurred during transaction re-transmission
0x67 Watchdog timeout while polling scrub busy after scrub being stopped
0x68 Watchdog timeout while polling scrub busy after scrub being enabled
0x69 Watchdog timeout while polling self refresh entry request from DC FSM
0x6A Watchdog timeout while polling self refresh exit request from DC FSM
0x6B Watchdog timeout while polling self refresh exit done from DC FSM
0x6C Calibration enable VTC timeout waiting for phy_rdy
0x6D Frequency switching enable VTC timeout waiting for phy_rdy
0x6E Restore calibration timeout waiting for XPLL lock signal
0x6F Restore calibration XPLL found calibration error
0x70 Restore calibration timeout waiting for BISC fixdly rdy signal
0x71 Restore calibration found zero rl dly qtr value after XPHY BISC
0x72 Restore calibration failed in enable VTC post sanity check 1
0x73 Restore calibration enable VTC timeout waiting for phy_rdy
0x74 CA calibration failed to find noise right edge while incrementing CA odelay by higher taps
0x75 CA calibration failed to find noise right edge while incrementing CA odelay
0x76 CA calibration failed in CA odelay centering stage
0x77 CA calibration failed to find noise right edge while incrementing CS odelay by higher taps
0x78 CA calibration failed to find noise right edge while incrementing CS odelay
0x79 CA calibration failed in CS odelay centering stage
0x7A Write DQ-DBI calibration failed to find right edge deep noise by incrementing DQ odelay
0x7B Write DQ-DBI calibration failed to find right edge deep noise by incrementing DBI odelay
0x7C Write DQ-DBI calibration failed to find right edge valid window by incrementing DBI odelay
0x7D Write DQ-DBI calibration failed to find right edge low noise by decrementing DBI odelay
0x7E Write DQ-DBI calibration failed to find right edge valid window by incrementing DQ odelay
0x7F Write DQ-DBI calibration failed to find right edge low noise by decrementing DQ odelay

Nibble location 1,2,3:

These three fields each contain nine bits of data. One bit for each nibble in an IO bank in the given triplet. Nibble location 3 [8:0] for the third IO bank. Nibble location 2 [8:0] for the second IO bank, and Nibble location 1 [8:0] for the first IO bank. A ‘1’ in any of these bit locations represents the nibble where a failure was detected associated with the error code defined earlier. Some calibration stages are done in parallel, so it is possible for multiple nibbles to be flagged.

Calibration Status/Stage:

This hex code represents nine bits of data.

See Table 1 for information on the contents.