Versal Devices with Dual Read Reorder Buffers - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Versal devices other than VC1902, VC1802, and VM1802 have two read reorder buffers (RROBs) in each DDRMC. This increases the number of read transactions the memory controller can operate on at the same time, increasing opportunities for reordering and improving DDR bus efficiency. This will have the biggest impact on random access workloads and dual DRAM channel configurations.

The following figure shows the dual 32-entry RROB in these devices. From the perspective of the memory controller, the two RROBs form a logical 64-entry RROB. This provides enough RROB entries to fill both DRAM controllers with read transactions. From the NoC perspective there are two independent 32-entry RROBs, each mapped to only two NSU ports. For good performance, read workloads that require the use of two or more NoC ports should select NoC ports so that both RROBs are involved. For example, for a configuration with two NoC ports, use ports 0 and 2 instead of 0 and 1.

Figure 1. Dual RROB Block Diagram