Write Centering (Complex) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
A more aggressive (complex) data pattern is used to stress the system for SI effects such as ISI and noise while centering the DQS within the DQ window at the memory.

This is accomplished as follows:

  1. Clear any delays from the DQ and DBI.
  2. Delay DQ and DBI to find a valid window for the byte lane (left side of valid window).
  3. Continue delaying DQ and DBI until the right side of noise region is found (right side of valid window).
  4. Calculate and center the DQ and DBI delays.
Table 1. Write Centering (Complex) Registers
Register Name Quantity Description
Fx_WRCMPLX_RIGHT_MARGIN_FCRSE Byte Taps of right side margin - 10 tap increments
Fx_WRCMPLX_RIGHT_MARGIN Byte Taps of right side margin
Fx_WRCMPLX_LEFT_MARGIN_FCRSE Byte Taps of left side margin - 10 tap increments
Fx_WRCMPLX_LEFT_MARGIN Byte Taps of left side margin
Fx_WRCMPLX_ODLY_DQS_FINAL Byte Final delay value for DQS
Fx_WRCMPLX_ODLY_DQ_FINAL DQ Pin Final delay value for DQ bit
Fx_WRCMPLX_ODLY_DBI_FINAL DBI Pin Final delay value for DBI bit