Write DQ/DBI Per-bit Deskew and Centering (Simple) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
The data and clock strobe need to be centered at the receiving memory to ensure the more reliable data transfer. The starting point is a 90 degree offset from DQS and from there adjust the delays on the DQ and DBI pins until the valid data window is found, then center the delays.

This is accomplished as follows:

  1. Find the valid DQ window using DQS delay.
  2. Revert the DQS delay if valid window not found.
  3. Find the valid DQ window using the DQ delay and then center the DQ bits.
  4. Find the valid DBI window using DQS delay.
  5. Revert the DQS delay if valid window not found.
  6. Find the valid DBI window using the DBI delay and then center the DBI bits.
Table 1. Write DQ/DBI Per-bit Deskew and Centering (Simple) Registers
Register Name Quantity Description
Fx_WRDQDBI_STG1_DQS_DELAY Byte DQS odelay after finding valid window by moving DQS
Fx_WRDQDBI_STG1_BYTE_STATUS 2 Value of 1 if a valid window is found. One bit per byte lane
Fx_WRDQDBI_STG1_BIT_STATUS DBI pins Value of 1 if a valid window is found
Fx_WRDQDBI_STG2_DQS_ODLY Byte Odelay for DQS after reverting
Fx_WRDQDBI_STG2_DQ_ODLY DQ bit Odelay for DQ after reverting
Fx_WRDQDBI_STG3_DQ_ODLY DQ bit Odelay value for the valid window using DQ delay
Fx_WRDQDBI_DESKEW_DQ_ODLY_FCRSE DQ bit Deskew delay 10-tap increments
Fx_WRDQDBI_DESKEW_DQ_ODLY DQ bit Deskew delay
Fx_WRDQDBI_STG4_DQS_DELAY DBI pin DQS Odelay value for the valid window
Fx_WRDQDBI_STG4_BYTE_STATUS 2 1 if a valid window is found. 1 bit per byte lane
Fx_WRDQDBI_STG5_DQS_ODLY DBI pin Odelay after reverting DQS
Fx_WRDQDBI_STG6_DBI_ODLY DBI pin DBI Odelay value for valid window using
Fx_WRDQDBI_DESKEW_DBI_ODLY_FCRSE DBI pin Deskew delay 10-tap increments
Fx_WRDQDBI_DESKEW_DBI_ODLY DBI pin Deskew delay
Fx_WRDQDBI_LEFT_MARGIN Byte Smallest margin left of center for the byte in Odelay taps
Fx_WRDQDBI_LEFT_EDGE_DQ DQ bit Odelay value for left edge of DQ
Fx_WRDQDBI_LEFT_EDGE_DBI DBI bit Odelay value for left edge of DBI
Fx_WRDQDBI_RIGHT_MARGIN_FCRSE Byte Right margin DQS Odelay with 10-tap increments
Fx_WRDQDBI_RIGHT_MARGIN Byte Smallest margin right of center for the byte in Odelay taps
Fx_WRDQDBI_RIGHT_EDGE_DQS Byte DQS Odelay value for the right edge
Fx_WRDQDBI_ODLY_DQS_FINAL Byte Final DQS Odelay value
Fx_WRDQDBI_ODLY_DQ_FINAL DQ bit Final DQ Odelay value
Fx_WRDQDBI_ODLY_DBI_FINAL DBI bit Final DBI Odelay value