When the write DBI option is selected for DDR4/LPDDR4, the pin itself is calibrated as a DM and write DBI are enabled at the end of calibration.
In all previous stages of calibration, data mask signals are driven low before and after the required amount of time to ensure they have no impact on calibration. Now, both the read and the writes have been calibrated and data mask can reliably be adjusted. If DM signals are not used within the interface, this stage of calibration is skipped.
During DM Calibration, a data pattern of
55555555_55555555 is first written to address 0x000 followed by a write to
the same address but with a data pattern of
BBBBBBBB_BBBBBBBB with DM asserted during the rising edge of DQS. A read
is then issued where the expected read back pattern is all
0xBs except for the data where DM was asserted. In these masked locations,
5 is expected. The same series of steps completed
during Write Per-Bit Deskew and Write DQS Centering is then completed but for the DM