Write latency calibration is required to align the write DQS to the correct CK edge. During write leveling, the write DQS is aligned to the nearest rising edge of CK. However, this might not be the edge that captures the write command. Depending on the interface type (UDIMM, RDIMM, LRDIMM, or component), the DQS could be up to three CK cycles earlier or aligned to the CK edge that captures the write command.
Write latency calibration makes use of the coarse tap in the
WL_RNK_REG of the XPHY for adjusting the write latency
on a per byte basis. Write leveling uses up a maximum of three coarse taps of the
XPHY delay ensuring each write DQS is aligned to the nearest clock edge. Memory
Controller provides the write data 1 tCK early to the PHY, which is then delayed by
write leveling up to one memory clock cycle. This means for the zero PCB delay case
of a typical simulation the data would be aligned at the DRAM without additional
delay added from write calibration.
Write latency calibration can only account for early data, because in the case where the data arrives late at the DRAM there is no push back on the controller to provide the data earlier. With 16 XPHY coarse taps available (each tap is 90°), four memory clock cycles of shift are available in the XPHY with one memory clock used by write leveling. This leaves three memory clocks of delay available for write latency calibration.
The figure shows the calibration flow to determine the setting required for each byte.
The write DQS for the write command is extended for longer than required to ensure the DQS is toggling when the DRAM expects it to clock in the write data. A specific data pattern is used to check when the correct data pattern gets written into the DRAM, as shown in the following figure.
In the example at the start of write latency calibration for the
given byte. the target write latency falls in the middle of the data pattern. The
returned data would be
55AA9966FFFFFFFF rather than
FF00AA5555AA9966. The write DQS and
data are delayed using the XPHY coarse delay and the operation is repeated, until
the correct data pattern is found or there are no more coarse taps available. After
the pattern is found, the amount of coarse delay required is indicated by
If the data pattern is not found for a given byte, the data pattern found is checked to see if the data at the maximum delay available still arrives too early (indicating not enough adjustment was available in the XPHY to align to the correct location) or if the first burst with no extra delay applied is already late (indicating at the start the data would need to be pulled back). The following data pattern is checked:
- Expected pattern on a per-nibble basis:
- Late Data Comparison:
- Early Data Comparison:
CAL_ERROR Decode for Write Latency Calibration
The status of Write Latency Calibration can also be determined by decoding the CAL_ERROR result according to the following table.
|Recommended Debug Step
|Could not find the data pattern given the amount of movement available.
|Write Latency found rank to rank skew greater than expected. Check margin for the byte for earlier stages of calibration. Probe the DQS/DQ signals (and DM if applicable).
|Check DQS and CK trace lengths for all the ranks. Ensure the maximum trace length is not violated. For debug purposes, try a lower frequency.
|Positive sanity check failed.
|Check read data margins from earlier stages of calibration. Check signal integrity during reads on the DQS and DQ.
|Initial write latency value before calibration.
|Rank and byte
|Write latency value.
|Minimum latency for the interface.
|Final Output Enable latency for the interface.
|Final write data latency for the interface.
|Final Output Enable latency.
|Final write data latency.
|Rank and byte
|Final coarse delay.