The data has been aligned to the DQS strobe, however the address
and command use a fly-by topology which allows for varying arrival times at the first
and the last memory component. This stage addresses the possible mismatch caused by
this.
This is accomplished as follows:
- Send a data pattern of all 0's, with 1's before the expected data and 1's after the expected data.
- Read the data back and compare with expected 0’s.
- Add or subtract coarse taps depending on the presence and location of 1’s in the read back data.
| Register Name | Quantity | Description |
|---|---|---|
| Fx_WRLAT_INIT_LATENCY | 1 | Initial write latency value before calibration |
| Fx_WRLAT_MATCH | Rank and byte | Write latency value |
| Fx_WRLAT_MIN_LATENCY | 1 | Minimum latency for the interface |
| Fx_WRLAT_XPI_OE_ALL_FINAL | 1 | Final Output Enable latency for the interface |
| Fx_WRLAT_XPI_WRDATA_ALL_FINAL | 1 | Final write data latency for the interface |
| Fx_WRLAT_PHY_OE_NIB_FINAL | Byte | Final Output Enable latency |
| Fx_WRLAT_PHY_DATA_NIB_FINAL | Byte | Final write data latency |
| Fx_WRLAT_WLDLYRNK_CRSE_FINAL | Rank and byte | Final coarse delay |