Write Leveling - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Each DQS is adjusted to be aligned with CK. The memory is placed in read levelling calibration mode, so the DQ values returned are the CK being sampled by the DQS at the memory. DQS is then adjusted to align with the CK at the memory.

This is accomplished as follows:

  1. Search for a stable 1 on the DQ by incrementing coarse taps.
  2. Decrement coarse taps to find a stable 0.
  3. Use fine taps to center on the noise region.

Table 1. Write Leveling Registers
Register Name Quantity Description
Fx_WRLVL_CRSE_STG1 Rank and byte Is this the Coarse Tap setting after finding the stable 1
Fx_WRLVL_OFFSET Rank and byte 90 degree offset in fine taps
Fx_WRLVL_CRSE_FINAL Rank and byte Stable 0 in coarse taps
Fx_WRLVL_NOISE_FCRSE Rank and byte Output delay value for valid-to-noise
Fx_WRLVL_FINE_LEFT Rank and byte The Fine Tap setting for the left side of the noise window
Fx_WRLVL_FINE_RIGHT Rank and byte The Fine Tap setting for the right side of the noise window
Fx_WRLVL_FINE_FINAL Rank and byte The final Fine Tap setting