Customizing and Generating the Core - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

This section includes information about using Xilinx® tools to customize and generate the core in the Vivado® Design Suite.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

Important: It is important to choose the exact part because characteristics such as speed grade, temperature grade, and silicon level affect the available features and performance limits of the serial transceivers. Limitations based on device characteristics are represented by the available choices when customizing the Wizard IP in the Vivado® Integrated Design Environment (IDE).
  1. In the Vivado Design Suite, create a new project or open an existing project that is configured to target one of the supported Virtex® UltraScale+™ devices which has a GTM transceiver.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.