Example Design Ports - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The ports shown in the following table are present on the example design top-level module, and are therefore package pins in the example project.

Table 1. Example Design Top-level Ports
Name Direction Clock Domain Description
refclk<i>_<j>_p Input N/A

Positive and negative inputs of the differential reference clock

refclk<i>_<j>_n Input N/A
gtm_ch<i><j>_rxn_in Input Serial

Positive and negative inputs of the transceiver channel differential serial data receiver, where:

<i>:0/1, <j>:dual* corresponding to the enabled duals.

gtm_ch<i><j>_rxp_in Input Serial
gtm_ch<i><j>_txn_out Output Serial

Positive and negative inputs of the transceiver channel differential serial data transmitter, where:

<i>:0/1, <j>:dual* corresponding to the enabled duals.

gtm_ch<i><j>_txp_out Output Serial
hb_gtwiz_reset_clk_freerun_in Input   Free-running clock, used by the example design and reset controller helper block.
Note: To alternatively use a differential clock input, add a second input port, instantiate an IBUFDS primitive driven by both the existing hb_gtwiz_reset_clk_freerun_in and that new port, and drive the input of the existing BUFG primitive with the output of that IBUFDS primitive instead of the hb_gtwiz_reset_clk_freerun_in port.
hb_gtwiz_reset_all_in Input Async Falling edge-triggered, active-High “reset all” input used by the reset controller helper block to initiate a full system reset sequence. Assumed to be de-bounced external to the device.
link_down_latched_reset_in Input Async Active-High signal used to reset the sticky link down indicator. Assumed to be de-bounced external to the device. Free-running clock, used by the example design and reset controller helper block for various system bring-up tasks. The example design top-level module globally buffers this single-ended clock input.
link_status_out Output hb_gtwiz_reset_clk_freerun_in Active-High, live indicator of link status based on combined PRBS match status across all example checking modules.
link_down_latched_out Output hb_gtwiz_reset_clk_freerun_in Active-High, sticky link down indicator. Set when link_status_out is Low and cleared when link_down_latched_reset_in is High.