Features - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English
  • Simple and intuitive feature selection flow.
  • Automatically sets transceiver parameters.
  • Example design with configurable PRBS generator, checker, and link status indicator to demonstrate functionality in simulation and hardware.
  • Support for GTM transceivers (GTM_DUAL) in Virtex® UltraScale+™ Virtex UltraScale+ devices.
  • Customization flow driven by the Vivado® Integrated Design Environment (IDE) providing high-level choices that configure supported transceiver features and automatically set primitive parameters, as appropriate.
  • Advanced configuration options to tune transceiver performance.
  • Available helper blocks to simplify common or complex transceiver usage, and the choice to either include or exclude each helper block from the core. Helper blocks excluded from the core are delivered as user-customizable starting points within the example design.
  • Synthesizeable example design with configurable pseudo-random binary sequence (PRBS) data generator, checker, and link status indicator logic to quickly demonstrate core and transceiver functionality in simulation.
    • Simulation test bench that monitors example design PRBS lock in external loopback, and indicates resulting link status. In case of FEC enabled test cases, indicative FEC data pattern generator is instantiated.
    • Additional convenience features, including differential reference clock buffer instantiation and wiring, and dual vector slicing.