The GTM Controller IP instantiates a MicroBlazeâ„¢ processor to control the sequencing of RXRESET and enhance link stability. gtm_cntrl_v1_0 IP is instantiated as a hierarchical IP inside the GTM Wizard IP to handle internal sequencing required over DRP ports. It is recommended that the default False option for BYPASS_GTM_CNTRL remains unchanged, except for advanced use cases where GTM Wizard is used for FEC only use-cases, that are typically used in GT loopback mode.
The GTM controller logic serves up to four duals within the same SLR region.
The number of duals selected in the GTM Wizard should be sequential and it must not
cross SLR boundaries. It is recommended to not perform any DRP operations while the
RX reset sequence is in progress. If any requirement to do DRP operations, it should
be ensured that gtwiz_sol_gpo
status is 0x3 or 0x7. Refer to
gtwiz_sol_gpo
port description below. Refer to
gtwiz_sol_gpo
port description.
Port Name | I/O | Clock | Description |
---|---|---|---|
ubclockper_rxcdr_lock_time[15:0] | Input | gtwiz_reset_clk_freerun_in (sync) | Configurable wait time for the GTM controller; Tie off to value 16'h0100. |
ch0_resetsol_en [3:0] | Input | gtwiz_reset_clk_freerun_in (sync) | Enables CH0 for DUALS [3:0] to use the GTM
controller; each bit enables the GTM controller for Dual3_Ch0 , Dual2_Ch0 , Dual1_Ch0 ,
Dual0_Ch0 .Note:
Drive used DualX_Ch0 to 1 and unused to 0.
Make sure that this port value is not changed when a reset request is in progress. If there is a reason to change the port value, pulse the datapath reset input of the helper logic. Ensure that the value of this port does not change while the reset sequence from reset helper block is in progress. The dynamic change of this port would not come in to effect until an additional RX datapath reset or gtrxreset_req_user is asserted for the GTM controller. |
ch1_resetsol_en [3:0] | Input | gtwiz_reset_clk_freerun_in (sync) | Enables CH1 for DUALS [3:0] to use the GTM controller. Each bit
enables the GTM controller for Dual3_Ch1 , Dual2_Ch1 ,
Dual1_Ch1 , Dual0_Ch1 .Note: Drive used DualX_Ch1 to 1 and unused to 0.
Make sure that this port value is not changed when a reset request is in progress. If there is a reason to change the port value, pulse the datapath reset input of the helper logic. Ensure that the value of this port does not change while the reset sequence from reset helper block is in progress. The dynamic change of this port would not come in to effect until an additional RX datapath reset or gtrxreset_req_user is asserted for the GTM controller. |
gtrxreset_req_user | Input | gtwiz_reset_clk_freerun_in (sync) | Requests the GTM controller to initiate an RX
reset sequence for channels specified by ch0_resetsol_en / ch1_resetsol_en . The recommended connection for this is from the reset controller helper logic output. |
gtwiz_sol_gpo[3:0] | Output | gtwiz_reset_clk_freerun_in (sync) | Status indicator logic from the GTM controller. Monitor this for the
GTM controller status to determine if the RX reset was successful:
Note:
|
es_fifo_request [7:0] | Input | ASYNC | Enables sampled Eye Scan for selected channel
{D3Ch1, D3Ch0, D2Ch1, D2Ch0, D1Ch1, D1Ch0, D0Ch1, D0Ch0} Note:
|
es_fifo_rclk | Input | ES FIFO Read clk It is recommended that you use the same source as freerun_clk in the GTM Wizard example design. |
|
es_fifo_axis_0_tready | Input | es_fifo_rclk | AXI4-Stream Interface: Indicates that the slave can accept a transfer in the current cycle. |
es_fifo_axis_0_tvalid | Output | es_fifo_rclk |
AXI4-Stream
Interface: Indicates that the master is driving a valid transfer. A
transfer takes place when both tvalid and tready are asserted. Note: tvalid also serves as the Empty flag for the
FIFO.
|
es_fifo_axis_0_tdata [15:0] | Output | es_fifo_rclk | AXI4-Stream Interface: Read Dataout from the FIFO. |
es_fifo_full | Output | es_fifo_rclk | Status flag that indicates sampled Eye Scan for selected channel has completed and FIFO is filled. |
es_fifo_axis_0_tlast | Output | es_fifo_rclk | Reserved. |
gtm_cntrl_ch0_rxclkrdy[3:0] | Output | RXUSRCLK2 | Status signal that indicates the stability of the rxusrclk2 when the GTM Controller logic performs internal DRP operations. |
gtm_cntrl_ch1_rxclkrdy[3:0] | Output | RXUSRCLK2 | Status signal that indicates the stability of the rxusrclk2 when the GTM Controller logic performs internal DRP operations. |
gtm_cntrl_in_fecrx0cwinc | Input | RXUSRCLK2 | Slice 0 codeword count increment. |
gtm_cntrl_in_fecrx0uncorrcwinc | Input | RXUSRCLK2 | Slice 0 uncorrected codeword count increment. |
gtm_cntrl_in_fecrx1cwinc | Input | RXUSRCLK2 | Slice 1 codeword count increment. |
gtm_cntrl_in_fecrx1uncorrcwinc | Input | RXUSRCLK2 | Slice 1 uncorrected codeword count increment. |
gtm_cntrl_in_fecrxln0biterr0to1inc | Input | RXUSRCLK2 | Lane0 bit error count increment (0 corrected to 1). |
gtm_cntrl_in_fecrxln0biterr1to0inc | Input | RXUSRCLK2 | Lane0 bit error count increment (1 corrected to 0). |
gtm_cntrl_in_fecrxln1biterr0to1inc | Input | RXUSRCLK2 | Lane1 bit error count increment (0 corrected to 1). |
gtm_cntrl_in_fecrxln1biterr1to0inc | Input | RXUSRCLK2 | Lane1 bit error count increment (1 corrected to 0). |
gtm_cntrl_in_fecrxln2biterr0to1inc | Input | RXUSRCLK2 | Lane2 bit error count increment (0 corrected to 1). |
gtm_cntrl_in_fecrxln2biterr1to0inc | Input | RXUSRCLK2 | Lane2 bit error count increment (1 corrected to 0). |
gtm_cntrl_in_fecrxln3biterr0to1inc | Input | RXUSRCLK2 | Lane3 bit error count increment (0 corrected to 1). |
gtm_cntrl_in_fecrxln3biterr1to0inc | Input | RXUSRCLK2 | Lane3 bit error count increment (1 corrected to 0). |
gtm_cntrl_in_fectrxln0lock | Input | RXUSRCLK2 | Lane 0 lock status. |
gtm_cntrl_in_fectrxln1lock | Input | RXUSRCLK2 | Lane 1 lock status |
gtm_cntrl_in_fectrxln2lock | Input | RXUSRCLK2 | Lane 2 lock status |
gtm_cntrl_in_fectrxln3lock | Input | RXUSRCLK2 | Lane 3 lock status |
Temperature [9:0] | Input | gtwiz_reset_clk_freerun_in (sync) | 10-bit ADC code from the SYSMON temperature sensor. Valid values must always be assigned. An example implementation of System Management Wizard IP is instantiated in the example design. If you are designing with the example designs, you do not need custom connections to temperature [9:0] ports. Designs using PAM4 modulation either with less than 12 dB insertion loss at Nyquist or with line rate greater than 53 Gb/s must integrate the SYSMON instantiation and provide valid values to the temperature [9:0] ports at all times; they cannot leave the port to be undriven or tie-off to 0's. |
GTM Wizard IP when in PAM4 enabled configurations, in general require RS-FEC implementations as part of the design, either using some custom parent IP implementations or the choice of using the integrated KP4 RS-FEC inside GTM_DUAL
The GTM Wizard IP requires the integrated KP4 RS-FEC for designs with PAM4 modulation and insertion loss of less than 12 dB (as set in the GTM Wizard Receiver Advanced Options) to be enabled. Designs that do not utilize the integrated KP4 RS-FEC for specified use mode must implement their own KP4 RS-FEC logic to provide equivalent statistics information as described in the RS FEC section in Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581). Note that the above ports are vectorized for each dual enabled in user design.