GTM Port Control Interface Description - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The Multi-Rate GTM Wizard IP provides controls of the GTM port values. The following settings are possible for each port.

User controlled
The gtm_mr_pval_ovrd_en input provides user override control for GTM control ports. There are 13 bits per dual and each bit enables user control of a subset of ports. The user is responsible for driving the port value through the associated port value input when the associated override bit is asserted. The mapping of ports to override bits is provided in Table 1.
gtm_ctrl controlled
The gtm_ctrl manages the port values for all ports that are not under user control and are not static across all rates. The port values of these ports are set based on rate selection.
Static
Ports that are not under user control and are static across all rates are set to the value specified in the default rate’s rules.vh file. Refer to the example design top commented code for bitwise definition of each of these port enablement conditions.
Table 1. GTM Port Control Override
Override Bit GTM Port Control
[4*(#DUALS-1)+0] bgbypassb, bgmonitorenb, bgpdb, bgrcalovrd, pllfbdiv
[4*(#DUALS-1)+1] pllrsvdin
[4*(#DUALS-1)+2] Pllresetmask, pllrefclksel, bgrcalovrdenb pllpd, rcalenb sdmtoggle
[4*(#DUALS-1)+3] sdmdata
[4*(#DUALS-1)+4] sdmdata
[4*(#DUALS-1)+5] ch0_pcsrsvdin, ch1_pcsrsvdin
[4*(#DUALS-1)+6] ch0_pmarsvdin, ch1_pmarsvdin
[4*(#DUALS-1)+7] ch0_rxoutclksel, ch1_rxoutclksel, ch0_rxpcsresetmask, ch1_rxpcsresetmask, ch0_loopback, ch1_loopback, ch0_resetovrd, ch1_resetovrd, ch0_rxcdrfreqos, ch1_rxcdrfreqos, ch0_rxcdrhold, ch1_rxcdrhold, ch0_rxeqtraining, ch1_rxeqtraining, ch0_rxcdrincpctrl, ch1_rxcdrincpctrl, ch0_rxcdrovrden, ch1_rxcdrovrden
[4*(#DUALS-1)+8] ch0_rxpmaresetmask, ch1_rxpmaresetmask
[4*(#DUALS-1)+9] ch1_rxresetmode, ch0_rxresetmode, ch0_rxprbsptn, ch1_rxprbsptn, ch0_rxusrstart, ch1_rxusrstart, ch0_rxusrstop, ch1_rxusrstop, ch0_rxpolarity ch1_rxpolarity, ch0_rxqprbsen, ch1_rxqprbsen, ch0_rxprbscntstop, ch1_rxprbscntstop
[4*(#DUALS-1)+10] ch0_txdrvamp, ch1_txdrvamp, ch0_txemppre, ch1_txemppre, ch0_txctlfirdat, ch1_txctlfirdat
[4*(#DUALS-1)+11] ch0_txempmain, ch1_txempmain, ch0_txemppre2, ch1_txemppre2, ch0_txemppost, ch1_txemppost, ch0_txinhibit, ch1_txinhibit
[4*(#DUALS-1)+12] ch0_txpcsresetmask, ch1_txpcsresetmask, ch0_txpmaresetmask ch1_txpmaresetmask, ch0_txoutclksel, ch1_txoutclksel, ch1_txprbsptn, ch0_txprbsptn, ch0_txqprbsen, ch1_txqprbsen, ch0_txprbsinerr, ch1_txprbsinerr ch0_txpolarity, ch1_txpolarity, ch0_txmuxdcdorwren, ch1_txmuxdcdorwren, ch0_txmuxdcdexhold, ch1_txmuxdcdexhold