|
Core Specifics |
| Supported Device Family
1
|
Virtex®
UltraScale+™
devices |
| Supported User Interfaces |
Not applicable |
| Resources |
Performance
|
| Provided with Core
|
| Design Files |
RTL |
| Example Design |
System Verilog |
| Test Bench |
System Verilog |
| Simulation Model |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide
|
| Supported S/W Driver |
N/A |
| Tested Design Flows
3
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide
|
| Support |
| Release Notes and Known
Issues |
Master Answer Record: 72071
|
| All
Vivado®
IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
- In this version of the GTM Wizard IP, SIP_GTM_DUAL instantiates the transceiver serial
ports as integers to showcase the PAM4 encoding levels. While this is masked as
logic wires at GTM_DUAL, the GTM Wizard
parent IP will have to perform a hierarchical access of these ports for simulation
purposes. So the legal values for transitions on these ports while in PAM4 mode
are: 0/1/2/3, while in NRZ mode they are: 0/3.
- Refer to the Simulation
section for mixed language simulation options.
|