Initialization Module - 1.0 English

The Wizard example design contains a module that demonstrates how initialization logic can be constructed to interact with and enhance the reset controller helper block to assist with successful system bring-up. The example initialization logic monitors for timely transceiver resource reset completion, retrying appropriate resets as necessary to mitigate problems with system bring-up such as clock or data connection readiness. It also optionally monitors data quality after the system is operational, resetting the receiver if the data is not considered to be “good.” The initialization module is an example and can be modified as necessary to suit your needs.

The example initialization module is implemented as a finite state machine that is activated with the first user-provided “reset all” pulse following device configuration. The module first monitors for timely completion of the transmitter PLL and datapath transceiver resources, pulsing an internal “reset all” signal to the reset controller helper block in the event that the transmitter resets do not complete in a reasonable time. Upon transmitter reset completion, the example initialization module similarly waits for timely completion of receiver PLL and datapath transceiver resources, pulsing an internal receiver PLL and datapath reset (or receiver datapath reset if a single PLL is used for both data directions) to the reset controller helper block in the event that the receiver resets do not complete in a reasonable time. For debug purposes, each reset assertion increments a retry counter up to a specified saturation point, and the retry counter is only cleared upon device configuration.

The example initialization module also contains a receive data good input. If an active-High indication of data quality drives this port, the initialization module automatically pulses the appropriate receiver reset to the reset controller helper block if the design has been successfully initialized but the receiver data good input is Low. In this way, the initialization module repeatedly attempts to re-establish good data reception in the event of its loss; for example, due to cable pull effects on the receiver. The following figure illustrates the initialization module state machine.

Figure 1. Example Initialization Module Finite State Machine

In the example design as delivered, the link status indicator signal directly drives the initialization module’s receive data good input port. Therefore, any loss of link causes repeated receiver reset attempts until the link is again established. This approach is useful for demonstrating link robustness in the face of system disruptions such as cable pull tests. If it is not desired, this optional behavior can be disabled by simply tying the initialization module’s receive data good port High.