Limitations of the Example Design - 1.0 English

The example design is the recommended means of simulating or implementing an instance of the Wizard IP core outside the context of your own system. It can also prove useful as a starting point for integrating the core into your system. However, it is quite simplistic, and the following limitations should be understood:

• The example design does not implement specific protocols to generate or check data. Fundamentally, raw PRBS data is generated and checked. For FEC enabled use cases, a default PCS pattern is sent which does not test all the IEEE 802.3 specified patterns. Also only FEC lock from the GTM_DUAL is checked for arrival for test pass/fail criteria.
• When the example design is simulated using the provided test bench, each transceiver channel is looped back from the serial data transmitter to the receiver. As such, data integrity can only be properly checked if the transmitter and receiver are configured for the same line rate and to use the same data coding. No rate adjustment schemes are used. If the transmitter and receiver line rates or data coding are configured differently from one another in your system, you might wish to cross-couple two appropriately-customized core instances and check for data integrity in hardware or in your own test bench. In such a setup, the transmitter of core instance A is rate and coding-matched to the receiver of core instance B, and vice versa.
• Example design needs an update for giving the port maps before bitstream generation, you need to consider the target board and update the location constraints accordingly.
• There are chances that the Example Design may not meet the timing in all configurations depending on the speed grade and IP configuration, please refer to UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) and try different implementation/synthesis strategies.
• SIP_GTM_DUAL does not model all the GT hard block functionalities. It is a high level abstraction model, and so, some of the features such as powerdown are not modeled by the simulation model.
• In case of Multi-rate use cases, since the generated GTM Wizard IP instance does not know the final target rate on which the desgin would run, it is recommended to manually add the xdc constraints for ch*txoutclk and ch*rxoutclk in the design as per your requirements.