Link Status Logic - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The Wizard example design instantiates an independent PRBS data checker module for each enabled transceiver channel. The combined and synchronized match signal is used by the link status logic, which produces a link status indicator using a simple state machine within the Wizard example design. To best represent the link health of the example design system, the link status indicator follows the combined PRBS match value but is resilient to occasional mismatches such as infrequent bit errors.

The link status state machine uses a leaky bucket algorithm to accumulate multiple consecutive clock cycles of combined PRBS matches, incrementing a link counter to its prescribed maximum before reporting that the link is up (indicated by link_status_out = 1). After the link is up, any PRBS mismatches cause a more rapid decrease in the link counter, such that bursts of mismatches or independent mismatches in close proximity quickly reduce the link counter to its prescribed minimum where the link is reported as down (indicated by link_status_out = 0). The logic operates continually, and therefore automatically attempts to recover from transient mismatches or regain link upon its loss. The following figure illustrates the behavior of the link counter and resulting link status in response to various PRBS checker conditions.
Figure 1. Link Counter and Link Status in Response to Various PRBS Checker Conditions

Whenever the link is down, including at the start of operation, the sticky link down indicator link_down_latched_out is set to 1. It can only be reset by assertion of the link_down_latched_reset_in input.