Link Status and Initialization - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The Wizard example design contains link status logic that indicates the current state of the PRBS checkers across all transceiver channels while remaining tolerant of occasional mismatches such as infrequent bit errors. The example design also includes an initialization module that is a demonstration of how logic can be constructed to interact with and enhance the reset controller helper block to assist with successful system bring-up. Together, the link status logic and the initialization module provide a robust demonstration of example design system bring-up, and work in coordination to both indicate link status and regain the link if it is lost.