Method 1 - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

Instantiate the GTM Wizard IP in the top-level Verilog and continue using the same model of hierarchical referencing as used in the wizard IP example design. The top-level stimulus and checker logic will be replaced by GTM parent IP VHDL designs. This method avoids accessing across hierarchical boundaries.

Figure 1. Method 1