Create an additional Verilog wrapper logic on top of the GTM Wizard IP. Then create a dummy port with integer in the declaration as shown below, and abstract the requirement to have hierarchical access from this level.
Note: This additional logic is to be
controlled under synthesis translate on/off pragma so that the synthesis behavior
remains the same.
Following is an example code snippet:
//--Port declaration of the GTM Wizard IP wrapper top in user design
input gtm_ch0_rxp_in ,
output gtm_ch0_txp_in,
………….
………….
//pragma translate_off
input integer gtm_ch0_rxp_integer,
output integer gtm_ch0_txp_integer,
……
……
//pragma translate_on
………….
………….
//--Logic inside the module definition
//pragma translate_off
always @(*)
begin
force u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMRXP_integer = gtm_ch0_rxp_integer;
force gtm_ch0_txp_integer = u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMTXP_integer;
end
//pragma translate_on
Figure 1. Example Code
