The GTM_DUAL UNISIM models the Secure IP ports as integer declarations, while
the GTM_DUAL UNISIM abstracts this as a logic wire for synthesis and placement tools.
Because the GTM transceiver is targeted to have PAM4 signaling, which needs to model
analog values of 0/1/2/3 (in case of PAM4) OR 0/3 (in case of NRZ), you need to
hierarchically probe the internal variable in the UNISIM. These are modeled as CH{0/1} _GTM{T/R}X{P/N}_integer (for example, CH0_GTMTXN_integer). Refer to the hierarchical force
mechanism used in the example design simulation top for references on how to access
these for simulation purposes.With 2020.1 and later Vivado releases,
a new feature is introduced where the tool generates a xil_dut_bypass
module which takes care of the hierarchical access of GTM_DUAL PAM4
serial ports for simulation purpose. If the default Vivado IP
settings option is used, then when launch_simulation is clicked, the
xil_dut_bypass module gets generated by querying the latest
hierarchical reference of the GTM_DUAL unisim and gives the same for
user view, this module can be instantiated in a system verilog based top file in
simulation sources for port mapping of user logic. If you decides to avoid this and
continue with the workarounds as shown below, then this option should be disabled in
project settings before IP/Example design generation, so as to mimic the behavior of
existing designs, where the requirement would be that the user designs manually query
the hierarchical paths and use them. A code excerpt from the simulation top file is as
shown below:
integer gtm_ch0_n;
integer gtm_ch0_p;
always @(*)
begin
force gtm_ch0_n = u_exdes_top.u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMTXN_integer;
force gtm_ch0_p = u_exdes_top.u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMTXP_integer;
force u_exdes_top.u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMRXN_integer = gtm_ch0_n ;
force u_exdes_top.u_gtm_wiz_ip_top.inst.dual0.gtm_dual_inst.CH0_GTMRXP_integer = gtm_ch0_p ;
end
