Port Descriptions - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The transcode IP block’s port definitions are shown in the following table. The width of the data buses varies depending on whether the block is configured in 50GE mode or 100GE mode. The stat_rx_err_count_inc input is driven by the GTM_DUAL’s FEC hard block and allows the counting of the symbol errors in order to detect and implement the hi-SER state and associated logic.

Table 1. Transcoder Helper Block Port Descriptions
Port Name Width (50G) Width (100G) I/O Description
tx_din 132 320 Input Transmit path data input

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

tx_din_start 1 1 Input Start of codeword on tx_din

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

tx_dout 160 320 Output Transmit path data output

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

rx_din 160 320 Input Receive path data input

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

rx_din_start 1 1 Input Start of codeword on rx_din

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

rx_din_is_am 1 1 Input Indicates alignment markers present on rx_din.
rx_din_flags 4 4 Input

Indicates status of data on rx_din

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

  • [0]: No error exists at RX FEC output
  • [1]: Error exists at RX FEC output
  • [2]: No error corrected at chien search
  • [3]: Error corrected at chien search
rx_dout 132 320 Output Receive path data output

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

stat_rx_err_count_inc 4 4 Input Symbol error count from RS decoder

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

ctl_rx_bypass_correction 1 1 Input Correction bypass configuration

This is exposed as the top-level port as "gtm_transcode_ctl_rx_bypass_correction"

ctl_rx_bypass_indication 1 1 Input Indication bypass configuration

This is exposed as the top-level port as "gtm_transcode_ctl_rx_bypass_indication"

stat_rx_hi_ser 1 1 Output Hi-SER status

This signal is handled internal to the GTM Wizard IP and it interfaces the GTM_DUAL UNISIM.

stat_rx_tcd_lock 1 1 Output TX block lock status (100G mode only)

This is exposed as the top-level port as "gtm_transcode_stat_rx_tcd_lock"

stat_tx_pcs_am_lock 1 1 Output TX AM lock status

This is exposed as the top-level port as "gtm_transcode_stat_tx_pcs_am_lock"

gtm_transcode_bypass_rx_core 1 1 Input reserved port, tie-off to 0 Future enhancement for GTM Switchable Ethernet configurations
gtm_transcode_bypass_tx_core 1 1 Input reserved port, tie-off to 0 Future enhancement for GTM Switchable Ethernet configurations

For more information, see AR 72110.