An example design can be generated for any customization of the UltraScale™ FPGAs Transceivers Wizard IP core. After you customize and generate a core instance, choose the Open IP Example Design Vivado® Integrated Design Environment (IDE) option for that instance. A separate Vivado project opens with the Wizard example design as the top-level module. The example design instantiates the customized core.
The purpose of the Wizard IP example design is to:
- Provide a simple demonstration of the customized core instance operating in simulation or in hardware through the use of a link status indicator based on PRBS generators and checkers.
- Provide a starting point for integrating the customized core into your system, including reference clock buffers and example system-level constraints.
The example design contains configurable PRBS generator and checker modules per transceiver channel that enable simple data integrity testing, and resulting link status reporting. As described in Test Bench, an included self-checking test bench simulates the example design in loopback, checking for link maintenance. The example design is also synthesizable.