Rate Change Port Description

The port list for the Multi-Rate GTM Wizard IP extends the catalog IP port list to include the rate change interface. The width of each rate change port (#DUALS) is determined by the number of duals selected during GUI customization. The following table provides more details.

Table 1. Rate Change Port Descriptions
Name	Width	I/O	Clock	Description
gtwiz_reset_all_ins⁽¹⁾	1	In	Async.	Asynchronous reset. When asserted, resets the entire IP core.
gtm_drpclk⁽¹⁾	1	In	N/A	Free-running clock used by the rate change feature.
gtwiz_sol_gpo⁽¹⁾	4	Out	gtm_drpclk	Status indicator logic from the GTM controller. Monitor this for the GTM controller status to determine if the RX reset was successful: 0x0 = GTM controller in reset 0x1 = GTM controller initialized/idle 0x3 = GTM controller completed an RX reset successfully 0x7 = GTM controller completed an RX Reset unsuccessfully Note: When the GTM controller is enabled, ensure that the status RX reset is successful. The DRP operations are not expected to be performed when the status of gtwiz_sol_gpo[3:0] is either 0 or 1, that is when the GTM controller reset sequence is in progress. The link behavior may not be reliable if any DRP operations are performed during this stage. You may require an additional reset pulse to get a clean link again. In case gtwiz_sol_gpo is 0x7, it is recommended to either do a full reset (reset_all_in) or rx_datapath_reset toggle on the GTM Reset helper block. It is also expected that the reset_all_in input is kept asserted until the freerun clock input of the Wizard is stable and toggling to ensure that the GTM controller doesn't go to unknown state where in the status of this port could be 0x1. Additional reset_all_in pulse could be required in cases where the stability of the input freerun clock is not ensured during the power on sequence. Bit 3 of this signal is used to indicate if the status of the GTM Controller is Busy (1) or Idle (0).
ch0_resetsol_en⁽¹⁾	#DUALS	In	gtm_drpclk	During RX Reset Calibration, indicates which duals ch0 require calibration upon assertion of `gtrxreset_req_user`. 0x1 = Enable calibration 0x0 = Disable calibration
ch1_resetsol_en⁽¹⁾	#DUALS	In	gtm_drpclk	During RX Reset Calibration, indicates which duals ch0 require calibration upon assertion of `gtrxreset_req_user`. 0x1 = Enable calibration 0x0 = Disable calibration
gtrxreset_req_user⁽¹⁾	1	In	dtm_drpclk	RX Reset Calibration Enable. When asserted, calibrate the receivers indicated by the `resetsol_en` inputs if the programmed rate deems it necessary.
gtm_mr_ratechg_en	1	In	gtm_drpclk	Rate change enable. Rising-Edge sensitive. Wait a minimum of 1600 `gtm_drpclk` clock cycles after `gtwiz_sol_gpo` == 0x3.
gtm_mr_rate_in	#DUALS⁽¹⁾8	In	gtm_drpclk	Specifies rate selection as defined by the rate table rules file. 8-bits per dual for up to 256 unique rates.
gtm_mr_rate_status	#DUALS⁽¹⁾8	Out	gtm_drpclk	Specifies current rate of each dual. 8-bits per dual for up to 256 unique rates.
gtm_mr_ratechg_done	#DUALS	Out	gtm_drpclk	Rate change completion status. 1-bit per dual. 1’b1 = Rate change completed. 1’b0 = Rate change in progress.
gtm_mr_autorxreset_en	#DUALS	In	gtm_drpclk	`gtm_ctrl rx` reset management enable. 1-bit per dual. 1’b1 = `gtm_ctrl` manages dual’s reset. 1’b0 = user manages dual’s reset.
gtm_mr_ratechg_reset_req	#DUALS	Out	gtm_drpclk	`gtm_ctrl` gt reset request. 1-bit per dual. Corresponding bit in `gtm_mr_autorxreset_en` must be 1’b1 to enable. Connect to reset helper block `reset_all` input.
gtm_mr_pval_ovrd_en	#DUALS⁽¹⁾13	In	gtm_drpclk	User port control override. 13-bits per dual. Each bit enables user control of the corresponding port. See GTM Port Control Interface Description below for further details.
ratetable_bram_rst	1	Out	gtm_drpclk	Rate table reset
ratetable_bram_clk	1	Out	gtm_drpclk	Rate table clock
ratetable_bram_en	1	Out	gtm_drpclk	Rate table enable
ratetable_bram_we	1		gtm_drpclk	Rate table write enable
ratetable_bram_addr	16	Out	gtm_drpclk	Rate table address
ratetable_bram_din	32	Out	gtm_drpclk	Rate table data input
ratetable_bram_dout	32	In	gtm_drpclk	Rate table data output
gtm_mr_user_rsvd_out	#DUALS⁽¹⁾16	Out	gtm_drpclk	Reserved.
Catalog GTM Wizard IP signals used by the rate change interface

Rate Change Port Description - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)