Rate Change Protocol Description - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The rate change protocol consists of four processes:

Power-On / System Reset
As with cores generated from the catalog GTM Wizard, multi-rate cores must undergo a reset process on power-up and system level reset. During this process, the entire subsystem is reset by asserting the gtwiz_reset_all_in, causing the core’s gtm_ctrl and duals to undergo a full reset. During this process and throughout all operation of the core, the gtm_drpclk input clock must be stable. The transition of gtwiz_sol_gpo from 0x0 to 0x1 indicates completion of the gtm_ctrl’s reset process. Additionally, the Reset Controller Helper Block is required to complete the reset process. For PAM4 rates, a RX Reset and Calibration step must be performed. See item A in Figure 1. Each dual will maintain the last rate configured when subject to subsequent gtwiz_reset_all_in events.
RX Reset and Calibration
This process must be run after power-on / system reset and after a rate change. As with the catalog IP, the GTM receivers’ must be calibrated to ensure optimal performance when configured for PAM4 rates. Assert the ch0/ch1_resetsol_en inputs for the desired duals and gtwiz_reset_rx_datapath_in to enable the process.
For the rate change case, gtwiz_sol_gpo must be 0x3 before asserting gtwiz_reset_rx_datapath_in and cleared after the gtwiz_sol_gpo 0x3->0x1 transition. The process is completed when gtwiz_sol_gpo is 0x3. See item E in Figure 1. The example design provides an example configuration using the Reset Controller Helper Block and the gtm_mr_ratechg_reset_req of gtm_ctrl to initiate the RX Reset Calibration.
Rate Change
A rate change is enabled by asserting gtm_mr_ratechg_en with gtm_mr_rate_in set to the desired rates for each dual. Acceptance of the request is indicated by a 0 in any bit of gtm_mr_ratechg_done, after which gtm_mr_ratechg_en must be cleared. The request is completed when gtm_mr_rate_status equals gtm_mr_rate_in. During each dual rate change, DRP and port settings are read from the rate table. See item C in Figure 1.
Auto RX Reset
When the optional gtm_mr_autorxreset_en is asserted with a rate change request, the core responds by asserting the associated bits of gtm_mr_ratechg_reset_req upon rate change completion. This output can be used as the reset to the reset helper block. Only the gtm_mr_autorxreset_en bits associated with a rate change should be set. See item D in the following figure. The example design leverages the gtm_mr_autorxreset_en feature to initiate the RX Reset Calibration.
Figure 1. Rate Change Protocol Waveform