Receiver User Clocking Network Helper Block - 1.0 English

The receiver user clocking network helper block is a simple module used to derive and buffer the appropriate clocks to drive the RXUSRCLK and RXUSRCLK2 inputs of one or more transceiver channels.

By default, the helper block source clock input port gtwiz_userclk_rx_srcclk_in is driven by either the RXOUTCLK port of the master transceiver channel.

As shown in the following figure, if RXUSRCLK and RXUSRCLK2 frequencies are identical (which is the case when the receiver user data width is narrower than or equal to the size of the internal data width), then only a single BUFG_GT is instantiated within the helper block. This buffer drives both gtwiz_userclk_rx_usrclk_out and gtwiz_userclk_rx_usrclk2_out helper block output ports, which are wired to the RXUSRCLK and RXUSRCLK2 input ports, respectively, of the appropriate transceiver channels. The helper block configures the BUFG_GT to divide the source clock down to the correct user clock frequency as required.

Figure 1. Receiver User Clocking Network Helper Block (with One BUFG_GT)

As shown in the following figure, if RXUSRCLK is twice the frequency of RXUSRCLK2 (which is the case when the receiver user data width is wider than the internal data width), then two BUFG_GT primitives are instantiated within the helper block. The helper block configures one BUFG_GT to divide the source clock down to the correct receiver datapath frequency and drive the gtwiz_userclk_rx_usrclk_out helper block output port, which is wired to the RXUSRCLK input port of the appropriate transceiver channels. The helper block configures the other BUFG_GT to divide the source clock down to the correct receiver user interface frequency and drive the gtwiz_userclk_rx_usrclk2_out helper block output port, which is wired to the RXUSRCLK2 input port of the appropriate transceiver channels.

Figure 2. Receiver User Clocking Network Helper Block (with Two BUFG_GT Primitives)

The helper block holds BUFG_GT primitive(s) in reset when the gtwiz_userclk_rx_reset_in user input is asserted. This reset input should be held High until the source clock input is known to be stable. When the reset input is released, the gtwiz_userclk_rx_active_out user indicator synchronously asserts, indicating an active user clock and allowing dependent helper blocks to proceed.

The helper block can be located either within the core or in the example design per user selection. If included within the core, wiring from the appropriate transceiver channel primitive RXOUTCLK output port(s) to the helper block gtwiz_userclk_rx_srcclk_in input port(s) is also internal to the core, but that clock signal is presented on the core interface as gtwiz_userclk_rx_srcclk_out.

Similarly, wiring between the helper block gtwiz_userclk_rx_usrclk_out and gtwiz_userclk_rx_usrclk2_out output ports and the transceiver channel primitives is internal to the core, but those helper block outputs are also presented on the core interface. If the helper block is located within the example design, then the relevant transceiver channel clock ports are enabled on the core interface so that the necessary signals can cross the core boundary.

For a description of all receiver user clocking network helper block ports, see Product Specification. For complete documentation on clocking the transceiver primitives, see Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581).