Receiver User Clocking Network Helper Block Ports - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The receiver user clocking network helper block provides a single interface with a source clock input port driven by a transceiver primitive-based output clock. Receiver user clocking network helper block ports can be identified by the prefix gtwiz_userclk_rx_. For guidance on the usage of the receiver user clocking network helper block, see Designing with the Core.

The receiver user clocking network helper block ports described in the following are present on the Wizard core instance when it is configured to locate the receiver user clocking network helper block in the core.

Table 1. Receiver User Clocking Network Helper Block Ports
Port Name I/O Clock Description
gtwiz_userclk_rx_reset_in Input Async User signal to reset the clocking resources within the helper block. The active-High assertion should remain until gtwiz_userclk_rx_srcclk_in/out is stable.
gtwiz_userclk_rx_srcclk_out Output   Transceiver primitive-based clock source used to derive and buffer the RXUSRCLK and RXUSRCLK2 outputs.
gtwiz_userclk_rx_usrclk_out Output   Drives RXUSRCLK of transceiver dual primitives. Derived from gtwiz_userclk_rx_srcclk_in/ out, buffered and divided as necessary by BUFG_GT primitive.
gtwiz_userclk_rx_usrclk2_out Output   Drives RXUSRCLK2 of transceiver channel primitives. Derived from gtwiz_userclk_rx_srcclk_in/out, buffered and divided as necessary by BUFG_GT primitive if required.
gtwiz_userclk_rx_active_out Output gtwiz_userclk_rx_ usrclk2_out Active-High indication that the clocking resources within the helper block are not held in reset.
gtwiz_userclk_rx_active_in Input Async When the clocks produced by the receiver user clocking network helper block are active, this active-High port must be asserted to allow dependent helper blocks within the core to operate. The receiver user clocking network helper block drives this port by default.
gtwiz_userclk_rx_srcclk_in Input N/A Transceiver primitive-based clock source used to derive and buffer RXUSRCLK and RXUSRCLK2 outputs.