These documents provide supplemental material useful with this guide:
- Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite Tutorial: Logic Simulation (UG937)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)
- UltraScale Devices Integrated Block for 100G Ethernet LogiCORE IP Product Guide (PG165)
- 100G IEEE 802.3bj Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG197) (registration required)
- 50G IEEE 802.3 Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG234) (registration required)
- IEEE Standard for Ethernet (IEEE Std 802.3-2015)
- Vivado Design Suite Tutorial: Logic Simulation (UG937)
- UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)