Reset Controller Helper Block - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The reset controller helper block simplifies the process of resetting and initializing the serial transceiver primitives. To operate, the helper block must be provided the free-running clock gtwiz_reset_clk_freerun_in that is toggling at the frequency specified during IP customization, prior to device configuration.

A single instance of the helper block is delivered with each instance of the Wizard IP core. Its user interface provides you with a simple means of initiating and monitoring the completion of transceiver reset procedures. Its transceiver interface connects to each transceiver primitive resource within the core instance.

The helper block contains three finite state machines:

Transmitter reset state machine
Resets the transmitter PLL and/or the transmitter datapath of all transceiver primitives, and indicates their completion.
Receiver reset state machine
Resets the receiver PLL and/or the receiver datapath of all transceiver primitives, and indicates their completion.
“Reset all” state machine
Controls the transmitter and receiver reset state machines and sequences them appropriately to reset all of the necessary transceiver primitives without redundant operations.

The transmitter and receiver reset state machines are independent of one another, and each can be initiated either directly through the user interface or by the “reset all” state machine using the reset all command. The reset all state machine is provided as a convenience and is useful for initial bring-up. However, it is not necessary to use if only independent transmitter and reset sequences are required.