Reset Controller Helper Block Ports - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The reset controller helper block contains a user interface and a transceiver interface. The user interface provides a simple means of initiating and monitoring the completion of transceiver reset procedures. The transceiver interface implements the signaling required to control the various transceiver primitive reset sequences.

Reset controller helper block user interface ports can be identified by the prefix gtwiz_reset_. For guidance on the usage of the reset controller helper block, see Designing with the Core.

The reset controller helper block user interface ports described in the following table are present on the helper block itself. It is directly accessible as the helper block is located in the example design.

Table 1. Port Descriptions
Port Name I/O Clock Description
gtwiz_reset_clk_freerun_in Input N/A Free-running clock used to reset transceiver primitives. Must be toggling prior to device configuration. See Performance for maximum frequency guidance.

Width = 1

gtwiz_reset_all_in Input Async User signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. The falling edge of an active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process. This also works as the master reset for the entire gtm_cntrl helper logic.

Width = 1

gtwiz_reset_tx_pll_and_datapath_in Input Async User signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.

Width = 1

gtwiz_reset_tx_datapath_in Input Async User signal to reset the transmit data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.

Width = 1

gtwiz_reset_rx_pll_and_datapath_in Input Async User signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.

Width = 1

gtwiz_reset_rx_datapath_in Input Async User signal to reset the receive data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.

Width = 1

gtwiz_reset_tx_done_out Output TXUSRCLK2 of TX master channel Active-High indication that the transmitter reset sequence of transceiver primitives as initiated by the reset controller helper block has completed.

Width = 1

gtwiz_reset_rx_done_out Output RXUSRCLK2 of RX master channel

Active-High indication that the receiver reset sequence of transceiver primitives as initiated by the reset controller helper block has completed.

Note: You must monitor the gtwiz_sol_gpo status for complete status when the GTM Controller helper block is present.

Width = 1

gtwiz_reset_userclk_rx_active_in Input Async When the RXUSRCLK and RXUSRCLK2 signals that drive transceiver primitives are active and stable, this active-High port must be asserted to allow the receiver reset sequence to complete.

Width = 1

gtwiz_reset_userclk_tx_active_in Input Async When the TXUSRCLK and TXUSRCLK2 signals that drive transceiver primitives are active and stable, this active-High port must be asserted for the transmitter reset sequence to complete.

Width = 1