The reset controller helper block transceiver interface ports described in the following table connect the reset controller helper block to transceiver primitives.
| Port Name | I/O | Clock | Description |
|---|---|---|---|
| gtpowergood_in | Input | Async | Logical AND of all GTPOWERGOOD signals produced
by transceiver dual logic. Width = 1 |
| txusrclk2_in | Input | Async | TXUSRCLK2 of master transceiver channel. Width = 1 |
| plllock_tx_in | Input | Async | Logical AND of all lock signals produced by PLLs
that clock the transmit datapath of transceiver dual primitives. Width = 1 |
| txresetdone_in | Input | Async | Logical AND of all TXRESETDONE signals produced
by transceiver dual primitives. Width = 1 |
| rxusrclk2_in | Input | Async | RXUSRCLK2 of master transceiver channel. Width = 1 |
| plllock_rx_in | Input | Async | Logical AND of all lock signals produced by PLLs
that clock the receive datapath of transceiver dual primitives. Width = 1 |
| rxresetdone_in | Input | Async | Logical AND of all RXRESETDONE signals produced
by transceiver dual primitives. Width = 1 |
| pllreset_tx_out | Output | gtwiz_reset_clk_freerun_in (used asynchronously) | Active-High signal fanned out to the reset ports
of all PLLs that clock the transmit datapath of transceiver dual
primitives. Width = 1 |
| txprogdivreset_out | Output | gtwiz_reset_clk_freerun_in (used asynchronously) |
Active-High signal fanned out to TXPROGDIVRESET port of all transceiver dual primitives. Width = 1 |
| gttxreset_out | Output | gtwiz_reset_clk_freerun_in (used asynchronously) | Active-High signal fanned out to GTTXRESET port
of all transceiver dual primitives. Width = 1 |
| txuserrdy_out | Output | gtwiz_reset_clk_freerun_in (used asynchronously) | Active-High signal fanned out to TXUSERRDY port
of all transceiver dual primitives. Width = 1 |
| pllreset_rx_out | Output | gtwiz_reset_clk_freerun_in (used asynchronously) | Active-High signal fanned out to the reset ports
of all PLLs that clock the receive datapath of transceiver channel
primitives. Width = 1 |
| rxprogdivreset_out | Output |
gtwiz_reset_clk_freerun_in (used asynchronously) |
Active-High signal fanned out to RXPROGDIVRESET
port of all transceiver dual primitives. Width = 1 |
| gtrxreset_out | Output |
gtwiz_reset_clk_freerun_in (used asynchronously) |
Active-High signal fanned out to GTRXRESET port of all transceiver dual primitives. Width = 1 |
| rxuserrdy_out | Output |
gtwiz_reset_clk_freerun_in (used asynchronously) |
Active-High signal fanned out to RXUSERRDY port
of all transceiver dual primitives. Width = 1 |
Note: All Input/Output ports which
are described as async are synchronized to
gtwiz_reset_clk_freerun_in in the example design. In user designs, all
asynchronous signals coming as inputs to the IP should be asserted for sufficient
time. This ensures that the synchronizers present inside the IP sampling on the
gtwiz_reset_clk_freerun_in identify the
toggles on these ports.