The transmitter and receiver reset state machines each have two entry points: one which causes the associated PLL(s) to be reset, followed by a reset of the datapath, and a second in which only the datapath is reset. The following figure illustrates the three reset controller helper block finite state machines and the reset sequences they control.
The transmitter reset state machine initiates a PLL reset followed by a
transmitter datapath reset when the
gtwiz_reset_tx_pll_and_datapath_in input is pulsed. All PLLs instantiated
by the core instance that are used to clock the transmitter datapath are reset in
response to this input. After all of these PLLs lock, the transmitter programmable
dividers and datapaths of all transceiver primitives are reset. If a PLL reset is not
needed, a transmitter datapath-only reset is initiated when the gtwiz_reset_tx_datapath_in input is pulsed. Regardless of the reset entry
point, the gtwiz_reset_tx_done_out indicator is
asserted synchronous to transmitter master channel TXUSRCLK2 upon completion of the
transmitter reset sequence for all transceiver primitives.
Likewise, the receiver reset state machine initiates a PLL reset
followed by a receiver datapath reset when the gtwiz_reset_rx_pll_and_datapath_in input is pulsed. All PLLs instantiated
by the core instance that are used to clock the receiver datapath are reset in response
to this input. When all these PLLs lock, the receiver datapaths of all transceiver
primitives are reset. If a PLL reset is not needed, a receiver datapath-only reset is
initiated when the gtwiz_reset_rx_datapath_in input is
pulsed. Regardless of the reset entry point, the gtwiz_reset_rx_done_out indicator is asserted synchronous to receiver
master channel RXUSRCLK2 upon completion of the receiver reset sequence for all
transceiver primitives.
gtwiz_reset_tx_pll_and_datapath_in and gtwiz_reset_rx_pll_and_datapath_in inputs. As both
transmitter and receiver datapaths are clocked by LCPLL resources, assertion of either
of those two inputs would reset the shared LCPLL of each transceiver Dual, causing
potentially-unintended link loss in the other data direction. Use these inputs with
caution, especially if PLL resources are shared with other core instances.The reset all state machine can be used to avoid just such redundant PLL
reset sequences. In addition, it resets the transmitter data direction before the
receiver data direction (which can improve data integrity in loopback or some other
circumstances) and is triggered by a simple one-input interface. The reset all state
machine does not sequence transceiver primitive reset signals itself. Rather, it
controls the transmitter and receiver reset state machines in the appropriate fashion
for your core customization—effectively controlling some sequence of gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, and gtwiz_reset_rx_datapath_in assertions. See the previous figure to
visualize the specific effects of the reset all state machine for your core
customization, noting that the reset all state machine is initialized by the falling
edge of the synchronized gtwiz_reset_all_in input.